Abstract: A new double-epitaxial structure for isolating deep (>5 .mu.m) trench capacitors (10, 10') with 1 .mu.m or less spacing (S) is disclosed. The structure comprises a thin, lightly doped upper epitaxial layer (16) on top of a thicker and more heavily doped bottom epitaxial layer (14). The low resistivity bottom epitaxial layer is intended to isolate trench capacitors of any depth. The high resistivity upper epitaxial layer is used for the CMOS periphery (22, 24) and can be selectively doped to achieve a near uniform concentration to isolate trench capacitors in the core region (20) surrounding the capacitors. Isolation between deep trenches at 1 .mu.m spacing has been demonstrated to be applicable for 4 Megabit and greater DRAM integration levels.

Abstract: A shallow capacitor cell is formed by using conventional integrated circuit processes to build a substrate mask having sublithographic dimensions. Multiple grooves, or trenches, are etched into the substrate using this mask. The capacitor dielectric layer and plate are then formed in the grooves.