Abstract: A transmitter comprises a first amplifier coupled to a first modulated local oscillator signal and a second amplifier coupled to a second modulated local oscillator signal. Digital to time conversion circuitry is configured to generate the first modulated local oscillator signal and the second modulated local oscillator signal such that the second modulated local oscillator signal has a delay to the first modulated local oscillator signal.

Abstract: Disclosed herein are devices, methods, and systems that relate to wireless communications architectures and, in particular, multi-band radio-frequency circuitry. Disclosed herein is a capacitive digital-to-analog converter (CDAC). The CDAC may include a plurality of circuits configured to receive a digital signal to be converted into an analog signal, wherein each circuit of the plurality of circuits may include: a variable capacitive element; and a driver configured to cause the variable capacitive element to be charged or discharged to convert the received digital signal into the analog signal.

Abstract: Techniques are disclosed to allow for a switched capacitor digital power amplifier (PA) that operates using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg.

Abstract: An electronic circuitry is proposed. The electronic circuitry comprises a directional coupler comprising a first port configured to receive an input signal from a signal source, a second port configured to output the input signal for transmission to a load, a third port configured to output a forward signal based on the input signal, and a fourth port configured to output a reverse signal based on a reflection of the input signal received at the second port. The electronic circuitry further comprises a Time-to-Digital converter, TDC, coupled to the third port and the fourth port. The TDC is configured to determine a phase difference between the forward signal and the reverse signal.

Abstract: For example, a phase shifter may include an input to receive an input clock signal having an input frequency and an input phase. For example, the phase shifter may include a quadrature phase-shift generator configured to generate a first signal and a second signal based on the input clock signal, the first and second signals having the input frequency, wherein a phase of the first signal is based on the input phase, wherein a phase of the second signal is shifted by a quadrature phase-shift relative to the phase of the first signal. For example, the phase shifter may include an output to provide an output based on the first signal and the second signal.

Abstract: For example, an apparatus may include an input to receive an input signal in a first voltage domain; a multi-mode power amplifier switchable between a plurality of power modes to generate an output signal based on the input signal; and an output to provide the output signal. For example, the multi-mode power amplifier may be configured to provide the output signal in the first voltage domain at a first power mode, and to provide the output signal in a second voltage domain at a second power mode. For example, a maximal voltage of the second voltage domain may be at least two times a maximal voltage of the first voltage domain.

Abstract: Techniques are disclosed to instruct how a switched capacitor digital power amplifier (PA) is configured to operate using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg. The digital PA has a topology that comprises a dual-feedback capacitive path that comprises a capacitive divider and a voltage stabilizing feedback path to selectively couple the capacitive divider to DC bias voltages.

Abstract: For example, a transmitter, e.g., for a wireless communication device, may be configured to transmit a wideband Radio Frequency (RF) Transmit (Tx) signal having a wide bandwidth of at least 80 Megahertz (MHz). For example, the transmitter may be configured to generate the wideband RF Tx signal having the wide bandwidth based on a baseband signal. The transmitter may be configured to generate the wideband RF Tx signal including a suppressed third harmonic and a suppressed fifth harmonic.

Abstract: A method for compensating signal nonlinearities includes generating a local oscillator (LO) signal and performing phase modulation of the LO signal to generate a phase-modulated LO signal. The phase modulation is based on applying at least one digital-to-time converter (DTC) code of a plurality of DTC codes to a rising edge signal portion and a falling edge signal portion associated with the LO signal. Nonlinearities associated with the rising edge signal portion and the falling edge signal portion are determined. The at least one DTC code is adjusted based on the nonlinearities.

Abstract: Techniques are described to address P-MOS bias temperature instability (BTI) stress issues within capacitive radio frequency digital-to-analog converter (CDAC) using a circuit architecture solution that functions to protect the transistors in various operating conditions. Techniques are disclosed that function to float one or both of the negative and positive power supply rail voltages higher or lower, respectively, for CDAC cells depending upon various operating scenarios. These scenarios include the transmitting state of individual CDAC cells and the transmitting state of the CDAC array in which the CDAC cell is implemented.

Abstract: Spiking neuron circuits and methods are provided in this disclosure. A spiking neuron may include a triggerable oscillator configured to generate an oscillator signal. The spiking neuron may further include a circuit configured to obtain an integration value based on received input spike signals. The spiking neuron may further include a leakage circuit configured to obtain a leakage value based on the oscillator signal. The spiking neuron may further include an oscillator activator configured to activate or deactivate the triggerable oscillator based on the leakage value and the integration value.

Abstract: Spiking neuron circuits and methods are provided in this disclosure. A spiking neuron may include a triggerable and frequency-controllable oscillator that is configured to generate an oscillator signal. The spiking neuron may further include a spike signal detector that is configured to generate spike detection signals in response to detection of input spike signals. The spike signal detector may generate the spike detection signals based on the oscillator signal. The spiking neuron may further include a neuron structure that is configured to provide an output spike signal based on the spike detection signals and the oscillator signal.

Abstract: A device may comprise: a storage for storing a reference output representing an output of an electrical circuit at a reference temperature; one or more processors, configured to: determine a temperature shift based on a comparison of an output of the electrical circuit sensed at a sensing temperature and the reference output; determine a plurality of coefficients of a model of the temperature shift, wherein the model implements one or more functions that associate the plurality of coefficients and a temperature with the temperature shift at the temperature.

Abstract: Various embodiments provide systems, devices, and methods for a multi-core digital power amplifier with an unbalanced power combiner. In one example, two or more cores are combined with a transformer section that has a first coupling coefficient and another two or more cores are combined with a second transformer section that has a second coupling coefficient that is different than the first coupling coefficient. The outputs of different cores may be cross-coupled with the primary inductors of the transformers. The digital power amplifier may provide an output power that is flat over a relatively wide operating range. Other embodiments may be described and claimed.

Abstract: A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. A number of capacitive digital analog converter (CDAC) cells of a power amplifier can be sized to provide defined power signals along a signal path. In response to an optimization component that is coupled to a CDAC cell of the plurality of CDAC cells operating in a high efficiency enable mode and the CDAC cell being powered off in an off mode, the optimization component can increase a power efficiency of the power amplifier by reducing an impedance of an output capacitor of the CDAC cell.

Abstract: Techniques are disclosed to allow for a switched capacitor digital power amplifier (PA) that operates using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg.

Abstract: A device for wireless communications can include a phase selector, a coarse delay line, and a digitally controlled edge interpolator (DCEI). The phase selector receives an input signal and is coupled to the coarse delay line. The coarse delay line can provide one of a plurality of delay ranges. A DCEI, connected to the coarse delay line can provide a fine delay output signal.

Abstract: An apparatus for interpolating between a first signal and a second signal is provided. The apparatus includes a first plurality of interpolation cells configured to generate a first interpolation signal at a first node. At least one of the first plurality of interpolation cells is configured to supply, based on a first number of bits of a control word, at least one of the first signal and the second signal to the first node. The apparatus further includes a second plurality of interpolation cells configured to generate a second interpolation signal at a second node. At least one of the second plurality of interpolation cells is configured to supply, based on a second number of bits of the control word, at least one of the first signal and the second signal to the second node.

Abstract: An apparatus for regulating a supply voltage supplied from a voltage source to a load via a supply line is provided. The apparatus includes a control circuit configured to generate a control signal based on a difference between a value of the supply voltage and a nominal value of the supply voltage. Further, the apparatus includes a switch circuit configured to couple a charged capacitive element to the supply line based on the control signal.

Abstract: An apparatus for interpolating between a first signal and a second signal is provided. The apparatus includes a first plurality of interpolation cells configured to generate a first interpolation signal at a first node. At least one of the first plurality of interpolation cells is configured to supply, based on a first number of bits of a control word, at least one of the first signal and the second signal to the first node. The apparatus further includes a second plurality of interpolation cells configured to generate a second interpolation signal at a second node. At least one of the second plurality of interpolation cells is configured to supply, based on a second number of bits of the control word, at least one of the first signal and the second signal to the second node.