Abstract: A device may comprise: a storage for storing a reference output representing an output of an electrical circuit at a reference temperature; one or more processors, configured to: determine a temperature shift based on a comparison of an output of the electrical circuit sensed at a sensing temperature and the reference output; determine a plurality of coefficients of a model of the temperature shift, wherein the model implements one or more functions that associate the plurality of coefficients and a temperature with the temperature shift at the temperature.

Abstract: This disclosure provides devices and methods for limiting the duration of pulses resulting from frequency modulation so as to provide for better propagation of a frequency doubler output within a communication device. The frequency doubler may be configured to receive a frequency doubler input and produce a modified frequency doubler output, wherein the frequency doubler includes a first flip-flop gate configured to receive a data input, a reset input, and a clock input and produce a first gate output; a first delay control configured to receive the gate output and produce a first delayed control output; and a first logic gate configured to receive the delayed control output and the frequency doubler input and produce a first logic gate output, wherein the modified frequency doubler output is based on the first logic gate output.

Abstract: A closed loop transmitter (Tx) calibration system is disclosed. The closed loop Tx calibration system comprises a transmitter circuit configured to generate a Tx output signal at a Tx output frequency based on a Tx local oscillator (LO) signal. The closed loop Tx calibration system further comprises a loop back (LPBK) receiver circuit coupled to the transmitter circuit and configured to downconvert the Tx output signal at the Tx output frequency to form an LPBK baseband signal at an LPBK intermediate frequency (IF), based on an LPBK LO signal. In some embodiments, the LPBK IF frequency is different from zero. In some embodiments, the closed loop Tx calibration system further comprises an LO generation circuit configured to generate the Tx LO signal and the LPBK LO signal from a single phase locked loop (PLL) source, based on utilizing a digital to time converter (DTC) circuit.

Abstract: An apparatus for regulating a supply voltage supplied from a voltage source to a load via a supply line is provided. The apparatus includes a control circuit configured to generate a control signal based on a difference between a value of the supply voltage and a nominal value of the supply voltage. Further, the apparatus includes a switch circuit configured to couple a charged capacitive element to the supply line based on the control signal.

Abstract: An apparatus for interpolating between a first signal edge and a second signal edge is provided. The apparatus includes a plurality of interpolation cells coupled to a common node. At least one of the plurality of interpolation cells is configured to supply, based on a control word, the first signal edge and/or the second signal edge to the common node. Further, the apparatus includes a control circuit configured to activate all of the plurality interpolation cells in a first mode of operation, and to deactivate part of the plurality of interpolation cells in a second mode of operation.

Abstract: An apparatus for interpolating between a first signal edge and a second signal edge is provided. The apparatus includes a plurality of interpolation cells coupled to a common node. At least one of the plurality of interpolation cells is configured to supply, based on a control word, the first signal edge and/or the second signal edge to the common node. Further, the apparatus includes a control circuit configured to activate all of the plurality interpolation cells in a first mode of operation, and to deactivate part of the plurality of interpolation cells in a second mode of operation.

Abstract: A method and apparatus for determining a difference between signal edges in two signals includes a multiple stage converter where each stage determines which of the two signals has an earlier signal edge, outputs a value corresponding to that determination, and then applies a delay to the earlier signal that is equal to half of the delay applied by the next previous stage. The stages examine smaller and smaller intervals to the sought-after signal edge. Each stage includes a plurality of logic elements. If all logic elements in the stage output the same signal, the edge position is clear. If some of the logic elements in the stage vote differently than others in the state due to differences in setup time for the different elements, the edge location has been found within the sensing band of the stage.

Abstract: A calibration system operates to calibrate or correct a digital-to-time converter (DTC) that comprises a detector component and a distortion correction component. The DTC can receive one or more signals and a digital code to generate a modulation signal by controlling an offset of the one or more signals based on the digital code. The detector component can comprise a TDC or another DTC that operates to measure a dynamic behavior in response to detecting nonlinearities of the modulation signal. The distortion correction component can generate a set of distortion data that removes the dynamic behavior from an output of the DTC based on the measurement.

Abstract: A calibration system operates to calibrate or correct a digital-to-time converter (DTC) that comprises a detector component and a distortion correction component. The DTC can receive one or more signals and a digital code to generate a modulation signal by controlling an offset of the one or more signals based on the digital code. The detector component can comprise a TDC or another DTC that operates to measure a dynamic behavior in response to detecting nonlinearities of the modulation signal. The distortion correction component can generate a set of distortion data that removes the dynamic behavior from an output of the DTC based on the measurement.

Abstract: Described herein are technologies related to an implementation of a time interleaved digital-to-time converter (DTC) topology to generate high frequency phase modulated local oscillator (LO) signals. A first and second DTC are connected to an oscillator where outputs of the two DTCs are combined to generate a phase modulated signal and the two DTCs have a frequency rate that is half the frequency rate of the phase modulated signal. The two DTCs can operate at a 50 percent or lower duty cycle.

Abstract: A system for calibrating a digital to time converter (DTC), includes a first DTC configured to receive a first digital input code and generate a first DTC output signal, and a second DTC configured to receive a second digital input code and generate a second DTC output signal. Further, the system includes a delay circuit configured to apply a first delay to the first DTC output signal to generate a first delayed DTC output signal and a phase detector circuit configured to determine a phase difference between the first delayed DTC output signal and the second DTC output signal, thereby generating a phase detector output. In addition, the system includes a calibration circuit configured to adjust the first digital input code of the first DTC to an adjusted first code that minimizes the phase detector output, based on a search algorithm.

Abstract: This application discusses, among other things, an interpolator architecture for digital-to-time converters (DTCs). In an example, an interpolator can include interpolation cells and retention cells configured provide an interpolated output based on at least two offset clock signals. In certain examples, an example interpolator can provide contention free control of the interpolator output with improved noise immunity.

Abstract: This application discusses, among other things, an interpolator architecture for digital-to-time converters (DTCs). In an example, an interpolator can include interpolation cells and retention cells configured provide an interpolated output based on at least two offset clock signals. In certain examples, an example interpolator can provide contention free control of the interpolator output with improved noise immunity.

Abstract: Embodiments of a system and method for synchronizing chains in a transceiver using central synchronization signals are generally described herein. In some embodiments, an RF signal having a reference frequency in a differential mode and a synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode are produced at a oscillator generation circuit. The RF signal having a reference frequency in a differential mode and the synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode are provided over each of a plurality of LO lines to a plurality of local LO generation circuit chains. Each synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode is extracted at the plurality of local LO generation circuit chains.

Abstract: Embodiments of a system and method for synchronizing chains in a transceiver using central synchronization signals are generally described herein. In some embodiments, an RF signal having a reference frequency in a differential mode and a synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode are produced at a oscillator generation circuit. The RF signal having a reference frequency in a differential mode and the synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode are provided over each of a plurality of LO lines to a plurality of local LO generation circuit chains. Each synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode is extracted at the plurality of local LO generation circuit chains.

Abstract: In general, in one aspect, the disclosure describes a method including determining a change in a lock state of a phase lock loop (PLL). Current provided to a charge pump (CP) is adjusted based on the change in the lock state of the PLL. The adjusting of the current is synchronized to occur during an idle state of the CP.

Abstract: In general, in one aspect, the disclosure describes a method including determining a change in a lock state of a phase lock loop (PLL). Current provided to a charge pump (CP) is adjusted based on the change in the lock state of the PLL. The adjusting of the current is synchronized to occur during an idle state of the CP.