Abstract: A shared USB device may be simultaneously configured and accessed by two or more USB hosts by using a multi-host capable device controller. The multi-host capable device may include separate upstream ports and buffers for each host, and may be configured with the capability to respond to USB requests from more than one host. The multi-host capable device may maintain a dedicated address, configuration, and response information for each host. Each host may therefore establish a dedicated USB connection with the sharing device without the sharing device having to be re-configured or re-enumerated each and every time the upstream hosts alternate accessing the USB device.

Abstract: An apparatus and method are presented for monitoring the performance of a microprocessor. The apparatus includes performance monitoring hardware incorporated within the microprocessor. The performance monitoring hardware includes a memory unit for storing performance data. The memory unit includes multiple memory locations, each memory location being accessed by a unique set of address signals. Circuitry within the performance monitoring hardware produces the address signals. In one embodiment, the performance monitoring hardware includes an event select register array and circuitry for producing a set of high order (i.e., most significant) address signals. The event select register array preferably includes several event select registers for storing binary codes corresponding to selected events. A performance data acquisition period is divided into multiple histogram time periods of equal length. The high order address signals partition the memory unit into sections.

Abstract: An apparatus and method are presented for monitoring the performance of a microprocessor. The apparatus includes performance monitoring hardware incorporated within the microprocessor. The performance monitoring hardware includes a memory unit for storing performance data. The memory unit includes multiple memory locations, each memory location being accessed by a unique set of address signals. Circuitry within the performance monitoring hardware produces the address signals. In one embodiment, the performance monitoring hardware includes an event select register array and circuitry for producing a set of high order (i.e., most significant) address signals. The event select register array preferably includes several event select registers for storing binary codes corresponding to selected events. A performance data acquisition period is divided into multiple histogram time periods of equal length. The high order address signals partition the memory unit into sections.

Abstract: A primary cache test system is supplied using a secondary cache that closely matches specifications of the primary cache. Coherency is maintained between the primary and secondary caches using inclusion by a write-once protocol. The test system includes software which suspends cache operations on receipt of an error signal from a secondary cache controller or by periodically pausing cache operations for cache operation monitoring. During suspension of cache operations, the software verifies the states of the primary cache against the states and data within the secondary cache. Signals on cache hit and hit-modified pins that are available on the microprocessor integrated circuit are monitored to detect various error conditions. Error analysis includes detection of invalid hits to the primary cache, incorrectly modified lines in the primary cache and misses to the primary cache that should be hits.

Abstract: A timing refresh circuit refreshes a timed circuit in a functionally equivalent manner, whether the timing refresh circuit is operated at a high frequency or a low frequency. The two-stage timing refresh circuit includes a counter and combinational logic, in combination, connected between a refresh timing signal generator and a control circuit. The counter is incremented for each refresh timing signal and decremented for each refresh cycle realized by the control circuit. The combinational logic converts the counter count to a refresh signal by generating a refresh request to the control circuit whenever a count is pending in the counter.

Abstract: A conditional wait state generator is interposed into the timing circuitry of a processor. The conditional wait state generator provides for analysis of a selected cycle type and for selection of the latency or number of wait states that is imposed during processor execution for that selected cycle type. In accordance with another aspect of the conditional wait state generator, a method of analyzing processor performance under specific operating conditions involves selection of a particular cycle type for testing and selection of a number of wait states that is imposed on processor operations for the selected cycle type and not for other cycle types. A conditional wait state generator is interposed into the timing circuitry of a processor and thereby imposes the selected conditions on the processor for analysis.

Abstract: An improved technique for gray scale compression of document image data is disclosed. The method comprises evaluating subportions of an image array as to relative levels of sameness and attempting to create sub-arrays having the same pixel value. Successively smaller sub-arrays are evaluated as to gray scale sameness unti 2.times.1 pixel arrays are encountered. At that time a code unique to each possible 2.times.1 pixel arrangement is stored. A high speed, real-time compression implementation is facilitated through described hardware. Document images are subdivided into 8 pixel by 512 pixel slices. As one document slice is stored in a first buffer RAM, a previously stored slice is compressed. As the pixel information is stored, tests are performed for 8.times.8 and 4.times.4 array sameness and one bit data stored according to the results of those tests. High speed compression is facilitated by querying the stored data as to the 8.times.8 and the 4.times.4 array sameness prior to further processing.

Abstract: A priority ordered multiple video object display system is disclosed for use with a raster scan display having a plurality of display locations on a plurality of display lines. The display system comprises means for generating a list of ordered video object data packets, and buffer means for storing the list of ordered data packets at locations spatially associated with respective display locations. Also included are means for varying the order in which the packets are written into the buffer means, and means for selectively suppressing zero overwrite for secondary writes to a single location in said buffer means during the construction of a common single display line stored within said buffer means. A method of presenting a video display is also disclosed.

Abstract: A line buffer system can display a large number of objects and a background in connection with the play of a video-type game. The system may be used with a microprocessor. Game data is transmitted from the microprocessor during a brief "handshake" operation which may occur at any time. The game data specifies the objects and background to be presented and the screen location of each. The objects and background, respectively, are stored as rectangular blocks in two memories. At least two buffers are provided, each buffer capable of storing data to represent one line of the picture. The system operates upon the game data to load the buffers in real time during picture drawing and just prior to picture drawing. One buffer then outputs a data stream to provide real time control of the drawing of one line of a picture. A flip feature provides for inverting any object or an entire picture about a vertical or horizontal axis, or both.