Patents by Inventor Atsuhiro Sato

Atsuhiro Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190348128
    Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
    Type: Application
    Filed: July 1, 2019
    Publication date: November 14, 2019
    Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
  • Patent number: 10461093
    Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: October 29, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Toshifumi Minami, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara, Hideyuki Kamata, Teppei Higashitsuji
  • Patent number: 10381084
    Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: August 13, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
  • Publication number: 20180342300
    Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
    Type: Application
    Filed: August 7, 2018
    Publication date: November 29, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
  • Patent number: 10074434
    Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: September 11, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
  • Publication number: 20180175055
    Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.
    Type: Application
    Filed: February 12, 2018
    Publication date: June 21, 2018
    Inventors: Toshifumi MINAMI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA, Hideyuki KAMATA, Teppei HIGASHITSUJI
  • Publication number: 20180108418
    Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
    Type: Application
    Filed: October 23, 2017
    Publication date: April 19, 2018
    Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
  • Patent number: 9893078
    Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: February 13, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Toshifumi Minami, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara, Hideyuki Kamata, Teppei Higashitsuji
  • Patent number: 9799403
    Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: October 24, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
  • Patent number: 9768189
    Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: September 19, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroshi Shinohara, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Toshifumi Minami, Hiroyuki Maeda, Shinji Saito, Hideyuki Kamata
  • Publication number: 20160358659
    Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
    Type: Application
    Filed: June 6, 2016
    Publication date: December 8, 2016
    Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
  • Patent number: 9437300
    Abstract: A semiconductor memory device includes first and second memory cell transistors, first and second word lines electrically connected to the first and second memory cell transistors, respectively, first and second transfer transistors. The first and second transistors are electrically connected to the first and second word lines, respectively. The sizes of the first transistor and the second transistor are different.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: September 6, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Kamata, Toshifumi Minami, Teppei Higashitsuji, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara
  • Publication number: 20160218109
    Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.
    Type: Application
    Filed: April 7, 2016
    Publication date: July 28, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi SHINOHARA, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Toshifumi Minami, Hiroyuki Maeda, Shinji Saito, Hideyuki Kamata
  • Patent number: 9361988
    Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: June 7, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
  • Patent number: 9337145
    Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: May 10, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Shinohara, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Toshifumi Minami, Hiroyuki Maeda, Shinji Saito, Hideyuki Kamata
  • Publication number: 20160071793
    Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.
    Type: Application
    Filed: March 10, 2015
    Publication date: March 10, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi SHINOHARA, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Toshifumi MINAMI, Hiroyuki MAEDA, Shinji SAITO, Hideyuki KAMATA
  • Publication number: 20160071870
    Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.
    Type: Application
    Filed: February 24, 2015
    Publication date: March 10, 2016
    Inventors: Toshifumi MINAMI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA, Hideyuki KAMATA, Teppei HIGASHITSUJI
  • Publication number: 20150262685
    Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
    Type: Application
    Filed: August 26, 2014
    Publication date: September 17, 2015
    Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
  • Publication number: 20150262669
    Abstract: A semiconductor memory device includes first and second memory cell transistors, first and second word lines electrically connected to the first and second memory cell transistors, respectively, first and second transfer transistors. The first and second transistors are electrically connected to the first and second word lines, respectively. The sizes of the first transistor and the second transistor are different.
    Type: Application
    Filed: August 26, 2014
    Publication date: September 17, 2015
    Inventors: Hideyuki KAMATA, Toshifumi MINAMI, Teppei HIGASHITSUJI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA
  • Publication number: 20150062843
    Abstract: According to one embodiment, a semiconductor device includes a cell portion and a peripheral portion, including: a substrate, a first insulating layer disposed on the substrate, a first conductive layer disposed on the first insulating layer, a second insulating layer disposed on the first conductive layer, and a second conductive layer disposed on the second insulating layer.
    Type: Application
    Filed: March 12, 2014
    Publication date: March 5, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Teppei HIGASHITSUJI, Toshifumi MINAMI, Hideyuki KAMATA, Atsuhiro SATO, Keisuke YONEHAMA