Patents by Inventor Atsuko Sakata

Atsuko Sakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180090438
    Abstract: According to some embodiments, a semiconductor device includes a substrate and an insulating film that is provided on the substrate. The device further includes a contact plug which includes a barrier metal layer provided in the insulating film, and a plug material layer provided in the insulating film, the barrier metal layer disposed between the plug material layer and the insulating film. The barrier metal layer includes at least a first layer including a first metal element and nitrogen, and a second layer including a second metal element different from the first metal element, and nitrogen.
    Type: Application
    Filed: March 3, 2017
    Publication date: March 29, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Masayuki KITAMURA, Atsuko SAKATA
  • Patent number: 9911753
    Abstract: According to one embodiment, an insulating layer is provided above a stairstep portion of a stacked body. A first cover film is provided between the stairstep portion and the insulating layer. The first cover film is of a material different from the insulating layer. A separation portion divides the stacked body and the insulating layer. A second cover film is provided at a side surface of the insulating layer on the separation portion side. The second cover film is of a material different from the insulating layer.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: March 6, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Masayuki Kitamura, Atsuko Sakata, Satoshi Wakatsuki, Takeshi Ishizaki, Daisuke Ikeno, Tomotaka Ariga
  • Patent number: 9905462
    Abstract: According to one embodiment, the stacked body includes a plurality of metal films, a plurality of silicon oxide films, and a plurality of intermediate films. The intermediate films are provided between the metal films and the silicon oxide films. The intermediate films contain silicon nitride. Nitrogen composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the metal films than on sides of interfaces between the intermediate films and the silicon oxide films. Silicon composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the silicon oxide films than on sides of interfaces between the intermediate films and the metal films.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: February 27, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Atsuko Sakata, Takeshi Ishizaki, Shinya Okuda, Kei Watanabe, Masayuki Kitamura, Satoshi Wakatsuki, Daisuke Ikeno, Junichi Wada, Hirotaka Ogihara
  • Patent number: 9831125
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a silicon film on an upper surface side, a lower surface side, and a side surface side of an air gap, while leaving part of the air gap between the silicon film formed on the upper surface side and the silicon film formed on the lower surface side. The method includes forming a metal film on a side surface of the slit. The method includes forming a plurality of metal silicide layers between the second layers by causing reaction between the metal film and the silicon film. The method includes removing unreacted part of the metal film formed on the side surface of the slit.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: November 28, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Wakatsuki, Hiroshi Nakazawa, Atsuko Sakata
  • Publication number: 20170316973
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.
    Type: Application
    Filed: July 17, 2017
    Publication date: November 2, 2017
    Inventors: Masayuki KITAMURA, Atsuko SAKATA, Makoto WADA, Yuichi YAMAZAKI, Masayuki KATAGIRI, Akihiro KAJITA, Tadashi SAKAI, Naoshi SAKUMA, Ichiro MIZUSHIMA
  • Patent number: 9793293
    Abstract: A semiconductor device includes a stacked body including a plurality of electrode layers stacked with an insulator interposed; a columnar portion provided in the stacked body and extending in a stacking direction of the electrode layers; and a first separation region provided in the stacked body and extending in a first direction. The stacked body includes a memory cell array and a staircase portion arranged in the first direction, the memory cell array including memory cells provided along the columnar portion, and the staircase portion including a plurality of terraces arranged along the first direction. The first separation region includes a first portion and a second portion in the staircase portion, the first portion having a first width in a second direction crossing the first direction, and the second portion having a second width in the second direction. The second width is narrower than the first width.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 17, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kosuke Horibe, Shinichi Nakao, Yasuhito Yoshimizu, Kouji Matsuo, Kei Watanabe, Atsuko Sakata
  • Patent number: 9779978
    Abstract: A method of manufacturing a semiconductor device uses a semiconductor manufacturing apparatus including a turn table allowing placement of at least first and second semiconductor substrates and being capable of moving positions of the first and the second semiconductor substrates by turning, a first film forming chamber, and a second film forming chamber. The first and the second film forming chambers are provided with an opening capable of loading and unloading the first and the second semiconductor substrates by lifting and lowering the first and the second semiconductor substrates placed on the turn table. The method includes transferring the first and the second semiconductor substrates between the first and the second film forming chambers by turning the turn fable and lifting and lowering the first and the second semiconductor substrates placed on the turn table; and forming a stack of films above the first and the second semiconductor substrates.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 3, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Kei Watanabe, Junichi Wada, Masayuki Kitamura, Takeshi Ishizaki, Shinya Okuda, Hirotaka Ogihara, Satoshi Wakatsuki, Daisuke Ikeno
  • Patent number: 9780111
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a film having semi-conductivity or conductivity, and a memory film. The stacked body includes a plurality of metal layers, a plurality of insulating layers, and a plurality of intermediate layers stacked on a major surface of the substrate. The film extends in the stacked body in a stacking direction of the stacked body. The memory film is provided between the film and the metal layers. The metal layers are tungsten layers and the intermediate layers are tungsten nitride layers. Or the metal layers are molybdenum layers and the intermediate layers are molybdenum nitride layers.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: October 3, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Takeshi Ishizaki, Junichi Wada, Atsuko Sakata, Kei Watanabe, Masayuki Kitamura, Daisuke Ikeno, Satoshi Wakatsuki, Hirotaka Ogihara, Shinya Okuda
  • Publication number: 20170263621
    Abstract: According to one embodiment, a stacked body includes a plurality of metal layers stacked with an insulator interposed. A semiconductor body extends in a stacking direction through the stacked body. A charge storage portion is provided between the semiconductor body and one of the metal layers. A metal nitride film has a first portion and a second portion. The first portion is provided between the charge storage portion and one of the metal layers. The second portion is thicker than the first portion and is provided between one of the metal layers and the insulator.
    Type: Application
    Filed: September 7, 2016
    Publication date: September 14, 2017
    Inventors: Satoshi WAKATSUKI, Atsuko SAKATA, Daisuke IKENO
  • Patent number: 9761531
    Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes interconnects each including a catalyst layer and a graphene layer thereon. The catalyst layer includes a first to fifth catalyst regions arranged along a first direction in order of the first to fifth catalyst regions. The first, third and fifth catalyst regions include upper surfaces higher than those of the second and fourth catalyst regions. Adjacent ones of the first to fifth catalyst regions are in contact with each other. A distance between the first and the third catalyst region and a distance between the third and fifth catalyst region are greater than a mean free path of graphene. The graphene layer includes a first graphene layer on the second catalyst region and a second graphene layer on the fourth catalyst region.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: September 12, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuro Saito, Masayuki Kitamura, Atsuko Sakata, Makoto Wada, Akihiro Kajita, Tadashi Sakai
  • Patent number: 9754793
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched, the mask layer containing tungsten and boron, a composition ratio of the tungsten being not less than 30%, patterning the mask layer, and performing a dry etching to the layer to be etched using the mask layer being patterned, and forming a hole or a slit in the layer to be etched.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: September 5, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi Nakao, Shunsuke Ochiai, Yusuke Oshiki, Kei Watanabe, Mitsuhiro Omura, Kosuke Horibe, Atsuko Sakata, Junichi Wada, Soichi Yamazaki, Masayuki Kitamura, Yuya Matsubara
  • Publication number: 20170229301
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.
    Type: Application
    Filed: September 18, 2012
    Publication date: August 10, 2017
    Inventors: Masayuki KITAMURA, Atsuko SAKATA, Makoto WADA, Yuichi YAMAZAKI, Masayuki KATAGIRI, Akihiro KAJITA, Tadashi SAKAI, Naoshi SAKUMA, Ichiro MIZUSHIMA
  • Patent number: 9728473
    Abstract: A method of manufacturing a semiconductor device includes forming a film along a surface of a semiconductor substrate in a first surface area state having a first surface area by supplying a reaction gas at a first flow rate. The method further includes detecting a transition from the first surface area state to a second surface area state having a second surface area different from the first surface area. The method still further includes forming the film by changing the flow rate of the reaction gas from the first flow rate to a second flow rate different from the first flow rate after detecting the transition from the first surface area state to the second surface area state.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: August 8, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Kitamura, Atsuko Sakata, Satoshi Wakatsuki
  • Publication number: 20170207236
    Abstract: According to one embodiment, an insulating layer is provided above a stairstep portion of a stacked body. A first cover film is provided between the stairstep portion and the insulating layer. The first cover film is of a material different from the insulating layer. A separation portion divides the stacked body and the insulating layer. A second cover film is provided at a side surface of the insulating layer on the separation portion side. The second cover film is of a material different from the insulating layer.
    Type: Application
    Filed: September 6, 2016
    Publication date: July 20, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki KITAMURA, Atsuko SAKATA, Satoshi WAKATSUKI, Takeshl ISHIZAKI, Daisuke IKENO, Tomotaka ARIGA
  • Publication number: 20170186766
    Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.
    Type: Application
    Filed: June 28, 2016
    Publication date: June 29, 2017
    Inventors: Ryohei KITAO, Atsuko Sakata, Takeshi Ishizaki, Satoshi Wakatsuki, Shinichi Nakao, Shunsuke Ochiai, Kei Watanabe
  • Publication number: 20170170069
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a silicon film on an upper surface side, a lower surface side, and a side surface side of an air gap, while leaving part of the air gap between the silicon film formed on the upper surface side and the silicon film formed on the lower surface side. The method includes forming a metal film on a side surface of the slit. The method includes forming a plurality of metal silicide layers between the second layers by causing reaction between the metal film and the silicon film. The method includes removing unreacted part of the metal film formed on the side surface of the slit.
    Type: Application
    Filed: April 18, 2016
    Publication date: June 15, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi WAKATSUKI, Hiroshi NAKAZAWA, Atsuko SAKATA
  • Patent number: 9673217
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, a semiconductor body, and a stacked film. The stacked body includes a plurality of tungsten layers and a plurality of alloy layers of tungsten and molybdenum. At least portions of the tungsten layers are stacked with an air gap interposed. The alloy layers are provided on surfaces of the tungsten layers opposing the air gap. The semiconductor body extends in a stacking direction through the stacked body. The stacked film is provided between the semiconductor body and the tungsten layers. The stacked film includes a charge storage portion.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: June 6, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Yohei Sato, Yasuhito Yoshimizu, Satoshi Wakatsuki, Takeshi Ishizaki, Masayuki Kitamura, Daisuke Ikeno, Tomotaka Ariga, Junichi Wada, Hiroshi Tomita, Hisashi Okuchi, Ryohei Kitao, Toshiyuki Sasaki, Kazuhito Furumoto
  • Patent number: 9613872
    Abstract: A method of manufacturing a semiconductor device includes forming a first metal containing a first conductivity-type impurity above a substrate provided with a first conductivity-type impurity region containing the first conductivity-type impurity and a second conductivity-type impurity region containing a second conductivity-type impurity; and forming a metal silicide containing the first metal by selectively causing, by thermal treatment, a reaction between the first metal and silicon contained in the substrate in the first conductivity-type impurity region.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: April 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Wakatsuki, Masayuki Kitamura, Atsuko Sakata, Kyoichi Suguro
  • Publication number: 20170092505
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched, the mask layer containing tungsten and boron, a composition ratio of the tungsten being not less than 30%, patterning the mask layer, and performing a dry etching to the layer to be etched using the mask layer being patterned, and forming a hole or a slit in the layer to be etched.
    Type: Application
    Filed: December 12, 2016
    Publication date: March 30, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shinichi NAKAO, Shunsuke OCHIAI, Yusuke OSHIKI, Kei WATANABE, Mitsuhiro OMURA, Kosuke HORIBE, Atsuko SAKATA, Junichi WADA, Soichi YAMAZAKI, Masayuki KITAMURA, Yuya MATSUBARA
  • Publication number: 20170062466
    Abstract: According to one embodiment, a semiconductor device includes an underlying metal film and a metal film. The underlying metal film is a tantalum-aluminum film having an aluminum content of more than 50 atomic % and less than 85 atomic %, a tungsten-zirconium film having a zirconium content of less than 40 atomic %, a tungsten-titanium film having a titanium content of less than 80 atomic %, or a tungsten film. The metal film is provided on the underlying metal film and in contact with the underlying metal film. The metal film contains at least one of tungsten and molybdenum, and has a main orientation of (100) or (111).
    Type: Application
    Filed: February 19, 2016
    Publication date: March 2, 2017
    Inventors: TAKESHI ISHIZAKI, ATSUKO SAKATA, SATOSHI WAKATSUKI