Patents by Inventor Atsumi Niwa

Atsumi Niwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11936996
    Abstract: Miniaturization of pixels is facilitated in a solid-state imaging element that detects presence or absence of an address event. The solid-state imaging element includes a plurality of detection pixels and a detection circuit. In the solid-state imaging element including the plurality of detection pixels and the detection circuit, each of the plurality of detection pixels generates a voltage signal according to a logarithmic value of a photocurrent. Furthermore, in the solid-state imaging element including the plurality of detection pixels and the detection circuit, the detection circuit detects whether or not a change amount of a voltage signal of a detection pixel indicated by an input selection signal among the plurality of detection pixels exceeds a predetermined threshold value.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: March 19, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Atsumi Niwa
  • Publication number: 20240072093
    Abstract: A solid-state imaging element (200) according to the present disclosure includes a light receiving substrate (201) and a circuit board (202). The light receiving substrate (201) includes a plurality of light receiving circuits (211) in which photoelectric conversion elements are provided. The circuit board (202) is bonded to the light receiving substrate (201) and includes a plurality of address event detection circuits (231) that respectively detects voltage changes output from the photoelectric conversion elements of the plurality of light receiving circuits (211). The circuit board (202) includes a first element region (501) and a second element region (502). In the first element region (501), a first transistor (T1) driven by a first voltage (VDD1) is arranged. In the second element region (502), a second transistor (T2) driven by a second voltage (VDD2) lower than the first voltage (VDD1) is arranged.
    Type: Application
    Filed: December 20, 2021
    Publication date: February 29, 2024
    Inventors: SHINICHI MIYAKE, KAZUYUKI TOMIDA, ATSUMI NIWA
  • Publication number: 20240061090
    Abstract: The present disclosure generally pertains to time-of-flight demodulation circuitry configured to: determine a light event pattern with an event-based light detection element of a plurality of event-based light detection elements; and determine, for a demodulation element of a plurality of demodulation elements, a timing for a demodulation signal to be applied to the demodulation element based on the light event pattern, wherein the demodulation element is associated with the event-based light detection element.
    Type: Application
    Filed: January 5, 2022
    Publication date: February 22, 2024
    Applicant: Sony Semiconductor Solutions Corporation
    Inventors: Cédric CARON, Sua KIM, Stefan ISLER, Kensei JO, Atsumi NIWA
  • Publication number: 20240064433
    Abstract: The present technology relates to an imaging element and an imaging device that facilitate miniaturization of pixels. The first substrate including a plurality of detection pixels that generates a voltage signal corresponding to a logarithmic value of a photocurrent, and the second substrate including a detection circuit that detects whether the change amount of the voltage signal of a detection pixel indicated by an inputted selection signal among the plurality of detection pixels exceeds a predetermined threshold or not are stacked, and an element constituting the detection circuit is disposed in each of a first region on a back surface side and a second region on a front surface side of the second substrate. The present technology can be applied to, for example, an imaging element that detects an address event for each pixel.
    Type: Application
    Filed: December 28, 2021
    Publication date: February 22, 2024
    Inventors: SHINICHI MIYAKE, KAZUYUKI TOMIDA, ATSUMI NIWA
  • Patent number: 11910108
    Abstract: Time deviation between event detection and gradation acquisition is reduced. A solid-state imaging apparatus according to an embodiment includes: a pixel array unit (300) including a plurality of pixel blocks (310) arrayed in a matrix; and a drive circuit (211) that generates a pixel signal in a first pixel block in which firing of an address event has been detected among the plurality of pixel blocks, each of the plurality of pixel blocks including a first photoelectric conversion element (331) that generates an electric charge according to an amount of incident light, a detection unit (400) that detects the firing of the address event based on the electric charge generated in the first photoelectric conversion element, a second photoelectric conversion element (321) that generates an electric charge according to an amount of incident light, and a pixel circuit (322, 323, 324, 325, 326) that generates a pixel signal based on the electric charge generated in the second photoelectric conversion element.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: February 20, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Atsumi Niwa, Motonari Honda
  • Patent number: 11895422
    Abstract: A mounting area in a solid-state imaging device that detects an address event. The solid-state imaging device includes a light receiving chip and a detection chip. In the solid-state imaging device including the light receiving chip and the detection chip, the light receiving chip includes a photodiode that photoelectrically converts incident light and generates a photocurrent. In addition, in the solid-state imaging device, the detection chip quantizes a voltage signal corresponding to the photocurrent generated by the photodiode in the light receiving chip and outputs the voltage signal as a detection signal.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: February 6, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Atsumi Niwa
  • Patent number: 11895411
    Abstract: It is an object to extend event signal detection periods. An imaging device according to the present technology includes a solid-state imaging device including a plurality of pixels each including a light-receiving portion that photoelectrically converts incident light to generate an electrical signal and a detection circuit that executes event signal detection by comparing the amount of change in the electrical signal generated by the light-receiving portion with a predetermined threshold value to obtain a detection result, and a control unit that performs control so that different pixels have different timing for an event detection period to cause the detection circuit to execute the event signal detection.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: February 6, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Atsumi Niwa, Yusuke Oike
  • Publication number: 20240027645
    Abstract: A sensing system includes a light emission control unit that controls light emission of a light source by using a light emission pattern determined in advance, a pixel array unit in which pixels that detect a change in a received light amount as an event and generate an event signal indicating presence or absence of detection of the event are two-dimensionally arranged, and a signal corrector that performs correction of the event signal on the basis of the light emission pattern.
    Type: Application
    Filed: December 23, 2021
    Publication date: January 25, 2024
    Inventor: ATSUMI NIWA
  • Patent number: 11876933
    Abstract: In a solid-state image sensor that detects an address event, the detection sensitivity for the address event is controlled to an appropriate value. The solid-state image sensor includes a pixel array unit and a control unit. In the solid-state image sensor, multiple pixel circuits are arranged in the pixel array unit, each detecting a change in luminance of incident light occurring outside a predetermined dead band as the address event. The control unit controls the width of the dead band according to the number of times the address event is detected in the pixel array unit within a fixed unit cycle.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: January 16, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Atsumi Niwa
  • Publication number: 20240007770
    Abstract: An object is to reduce a circuit scale in a solid-state imaging element that detects an address event. The solid-state imaging element is provided with a plurality of photoelectric conversion elements, a signal supply unit, and a detection unit. In this solid-state imaging element, each of the plurality of photoelectric conversion elements photoelectrically converts incident light to generate a first electric signal. Furthermore, in the solid-state imaging element, the detection unit detects whether or not a change amount of the first electric signal of each of the plurality of photoelectric conversion elements exceeds a predetermined threshold and outputs a detection signal indicating a result of the detection result.
    Type: Application
    Filed: May 3, 2023
    Publication date: January 4, 2024
    Inventors: Atsumi Niwa, Yusuke Oike
  • Publication number: 20230362503
    Abstract: Solid state imaging devices and electronic devices are disclosed. In one example, an imaging device includes photoelectric conversion sections arranged on a first chip and at least a part of each of detection circuits, an arbiter, and a signal processing circuit arranged on a second chip stacked on the first chip. A first region in the first chip in which the photoelectric conversion sections is arrayed and a second region in the second chip in which at least a part of each of the detection circuits is arrayed are at least partially superimposed in a stacking direction, and a logic circuit including the arbiter and the signal processing circuit is arranged in a third region at least partially adjacent to the second region in the second chip.
    Type: Application
    Filed: October 14, 2021
    Publication date: November 9, 2023
    Inventors: Atsushi Muto, Shinichirou Etou, Atsumi Niwa, Masafumi Yamashita
  • Publication number: 20230283926
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Application
    Filed: May 16, 2023
    Publication date: September 7, 2023
    Applicant: SONY GROUP CORPORATION
    Inventors: Atsumi NIWA, Yosuke UENO, Shimon TESHIMA, Daijiro ANAI, Yoshinobu FURUSAWA, Taishin YOSHIDA, Takahiro UCHIMURA, Eiji HIRATA
  • Publication number: 20230247314
    Abstract: Suppressing a dead period at the time of mode switching. A solid-state imaging device includes: a plurality of pixels (300) that each outputs a luminance change of incident light; and a detection circuit (305) that outputs an event signal based on the luminance change output from each of the pixels, in which each of the pixels includes: a photoelectric conversion element (311) that generates a charge according to an incident light amount; a logarithmic conversion circuit (312, 313) that is connected to the photoelectric conversion element and converts a photocurrent flowing out of the photoelectric conversion element into a voltage signal corresponding to a logarithmic value of the photocurrent; and a first transistor (318) having a drain connected to a sense node of the logarithmic conversion circuit.
    Type: Application
    Filed: April 23, 2021
    Publication date: August 3, 2023
    Inventors: Tsutomu Imoto, Yusuke Ikeda, Atsumi Niwa, Atsushi Suzuki, Shinichirou Etou, Kenichi Takamiya, Takuya Maruyama, Ren Hiyoshi
  • Publication number: 20230247316
    Abstract: A solid-state imaging device according to an embodiment includes: pixel circuits, each of the pixel circuits including: a generation unit (31) generating a voltage corresponding to a logarithmic value of a photocurrent; a capacitor (C1) having a first electrode to which the voltage generated by the generation unit is applied; a first amplifier (40a) having a first input terminal, which is connected to a second electrode of the capacitor, and a second input terminal, to which a first reference voltage (VbA0) is applied to, to output a comparison result obtained by comparing the voltage applied to the first input terminal with the voltage applied to the second input terminal; a switch unit (43) controlling a connection between the output of the first amplifier and the first input terminal; and a second amplifier (40b) having a third input terminal, to which the output of the first amplifier is connected, and a fourth input terminal, to which a second reference voltage (VbA1) is applied, to output a comparison r
    Type: Application
    Filed: June 28, 2021
    Publication date: August 3, 2023
    Inventors: TERUKAZU TANAKA, ATSUMI NIWA
  • Publication number: 20230247329
    Abstract: Provided is an image sensor including: a pixel section configured to include a plurality of pixels arranged therein; and an AD conversion unit configured to perform analog-to-digital (AD) conversion on a pixel signal on the basis of a result of comparison between a first voltage of a signal, which is obtained by adding, via capacitances, the pixel signal of the pixel and a reference signal that linearly changes in a direction opposite to the pixel signal, with a second voltage serving as a reference.
    Type: Application
    Filed: April 7, 2023
    Publication date: August 3, 2023
    Applicant: Sony Semiconductor Solutions Corporation
    Inventors: Atsumi Niwa, Tomonori Yamashita, Takashi Moue, Yosuke Ueno
  • Publication number: 20230217130
    Abstract: There is provided a solid-state image pickup element including: a photodiode configured to convert incident light into a photocurrent; an amplification transistor configured to amplify a voltage between a gate having a potential depending on the photocurrent and a source having a predetermined reference potential and output the amplified voltage from a drain; and a potential supply section configured to supply an anode of the photodiode and a back-gate of the amplification transistor with a predetermined potential lower than the reference potential.
    Type: Application
    Filed: September 27, 2022
    Publication date: July 6, 2023
    Inventor: Atsumi Niwa
  • Patent number: 11696053
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: July 4, 2023
    Assignee: SONY GROUP CORPORATION
    Inventors: Atsumi Niwa, Yosuke Ueno, Shimon Teshima, Daijiro Anai, Yoshinobu Furusawa, Taishin Yoshida, Takahiro Uchimura, Eiji Hirata
  • Publication number: 20230209218
    Abstract: Solid-state imaging devices are disclosed. In one example, a solid-state imaging device includes detection pixels that each output a luminance change of incident light, a detection circuit that outputs an event signal based on the luminance change, and a first common line connecting the detection pixels to each other. Each of the detection pixels may include a photoelectric conversion element, a logarithmic conversion circuit that outputs a voltage signal corresponding to a logarithmic value of photocurrent from the photoelectric conversion element, a first circuit that outputs a luminance change of incident light based on the voltage signal, a first transistor connected between the photoelectric conversion element and the logarithmic conversion circuit, and a second transistor connected between the photoelectric conversion element and the first common line. The detection circuit includes a second circuit that outputs the event signal based on the luminance change output from each of the detection pixels.
    Type: Application
    Filed: April 26, 2021
    Publication date: June 29, 2023
    Inventors: Takuya Maruyama, Tsutomu Imoto, Atsumi Niwa
  • Patent number: 11659304
    Abstract: An object is to reduce a circuit scale in a solid-state imaging element that detects an address event. The solid-state imaging element is provided with a plurality of photoelectric conversion elements, a signal supply unit, and a detection unit. In this solid-state imaging element, each of the plurality of photoelectric conversion elements photoelectrically converts incident light to generate a first electric signal. Furthermore, in the solid-state imaging element, the detection unit detects whether or not a change amount of the first electric signal of each of the plurality of photoelectric conversion elements exceeds a predetermined threshold and outputs a detection signal indicating a result of the detection result.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: May 23, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Atsumi Niwa, Yusuke Oike
  • Patent number: 11659291
    Abstract: Stability of a current-voltage conversion circuit is increased in a solid-state imaging element that converts photocurrent to a voltage signal. A photodiode photoelectrically converts incident light and generates photocurrent. A conversion transistor converts photocurrent to a voltage signal and outputs the voltage signal from a gate. A current source transistor supplies predetermined constant current to an output signal line connected to the gate. A voltage supply transistor supplies a certain voltage corresponding to the predetermined constant current from the output signal line to a source of the conversion transistor. A capacitance is connected between the gate and the source of the conversion transistor.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: May 23, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Atsumi Niwa