Patents by Inventor Atsumi Niwa

Atsumi Niwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200053308
    Abstract: Provided is an image sensor including: a pixel section configured to include a plurality of pixels arranged therein; and an AD conversion unit configured to perform analog-to-digital (AD) conversion on a pixel signal on the basis of a result of comparison between a first voltage of a signal, which is obtained by adding, via capacitances, the pixel signal of the pixel and a reference signal that linearly changes in a direction opposite to the pixel signal, with a second voltage serving as a reference.
    Type: Application
    Filed: February 19, 2018
    Publication date: February 13, 2020
    Applicant: Sony Semiconductor Solutions Corporation
    Inventors: Atsumi Niwa, Tomonori Yamashita, Takashi Moue, Yosuke Ueno
  • Publication number: 20200021769
    Abstract: The present technology is provided to accurately correct uneven luminance while suppressing an increase in the size of the solid-state imaging element. A pixel array unit includes a plurality of lines each including a predetermined number of pixels each being arrayed in a predetermined direction. An analog-to-digital conversion unit includes more than the predetermined number of analog-to-digital converters that convert analog signals into digital signals. A scanning circuit controls to sequentially select the plurality of lines and output more than the predetermined number of analog signals to the analog-to-digital conversion unit every time the line is selected. A correction unit performs black level correction processing on the digital signal.
    Type: Application
    Filed: October 27, 2017
    Publication date: January 16, 2020
    Inventors: ATSUMI NIWA, SHIZUNORI MATSUMOTO, EIJI HIRATA
  • Publication number: 20200007806
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Application
    Filed: September 4, 2019
    Publication date: January 2, 2020
    Applicant: SONY CORPORATION
    Inventors: Atsumi NIWA, Yosuke UENO, Shimon TESHIMA, Daijiro ANAI, Yoshinobu FURUSAWA, Taishin YOSHIDA, Takahiro UCHIMURA, Eiji HIRATA
  • Publication number: 20190305792
    Abstract: The present technology relates to a sensor, a driving method, and an electronic device that are capable of improving the dynamic range and noise of AD conversion. An AD conversion unit includes a comparator configured to compare an electric signal with a reference signal having a variable level, and performs AD conversion of the electric signal by using a result of the comparison between the electric signal and the reference signal by the comparator. An attenuation unit attenuates the electric signal supplied to the comparator in accordance with the amplitude of the electric signal. The present technology is applicable to, for example, a case where AD conversion is performed on an electric signal.
    Type: Application
    Filed: July 14, 2017
    Publication date: October 3, 2019
    Inventors: MASAKO HASEGAWA, RYUTA OKAMOTO, TOMONORI YAMASHITA, ATSUMI NIWA, YOSUKE UENO
  • Patent number: 10432884
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: October 1, 2019
    Assignee: Sony Corporation
    Inventors: Atsumi Niwa, Yosuke Ueno, Shimon Teshima, Daijiro Anai, Yoshinobu Furusawa, Taishin Yoshida, Takahiro Uchimura, Eiji Hirata
  • Publication number: 20190260385
    Abstract: The present disclosure relates to a solid-state imaging apparatus and electronic equipment which can realize operation with lower power consumption in a sensing mode. A solid-state imaging apparatus has an A/D conversion unit that A/D converts a pixel signal and an oscillator that generates a second internal clock with a frequency lower than that of a first internal clock obtained by multiplying an external clock, in which the A/D conversion unit is configured to operate, when operating by the second internal clock, with resolution lower than resolution of A/D conversion when operating by the first internal clock. The present disclosure can be applied to, for example, a CMOS image sensor.
    Type: Application
    Filed: July 7, 2017
    Publication date: August 22, 2019
    Inventor: ATSUMI NIWA
  • Publication number: 20190238764
    Abstract: The present disclosure relates to a solid-state imaging device, a solid-state imaging device operating method, an imaging apparatus, and an electronic apparatus that can realize an image at a low resolution with low power consumption without deteriorating imaging characteristics of all pixels. A floating interconnection line connecting FDs (floating diffusions) each set in a unit of shared pixels including at least one or more pixels, the FDs being provided in each column having a predetermined column number, and a switch changing over between connection and disconnection of the floating interconnection line to and from the FDs are provided. In addition, the switch changes over between the connection and the disconnection between the FDs and the floating interconnection line in response to a resolution that is a low resolution. The present disclosure can be applied to a solid-state imaging device.
    Type: Application
    Filed: June 30, 2017
    Publication date: August 1, 2019
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Atsumi NIWA, Oichi KUMAGAI, Shinichiro FUTAMI, Bostamam ANAS, Masahiko NAKAMIZO
  • Publication number: 20180287599
    Abstract: The present technology relates to a controller, a control method, an AD converter, and an AD conversion method by which settling can be improved. The controller includes: a first current source that generates an output signal corresponding to an input signal; a second current source that supplies a current to charge a predetermined capacitance; and a control unit that controls the current supplied from the second current source to the predetermined capacitance, where the first current source and the second current source are each formed of a transistor. The controller further includes a supply unit that supplies a current flowing to the first current source and the second current source, where the current flowing to the first current source and the second current source is proportional to a current flowing in the supply unit. The present technology can be applied to an AD converter included in an imaging apparatus.
    Type: Application
    Filed: October 29, 2015
    Publication date: October 4, 2018
    Inventors: Kazutoshi TOMITA, Atsumi NIWA
  • Publication number: 20180270438
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Application
    Filed: May 23, 2018
    Publication date: September 20, 2018
    Applicant: SONY CORPORATION
    Inventors: Atsumi NIWA, Yosuke UENO, Shimon TESHIMA, Daijiro ANAI, Yoshinobu FURUSAWA, Taishin YOSHIDA, Takahiro UCHIMURA, Eiji HIRATA
  • Patent number: 10021335
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: July 10, 2018
    Assignee: Sony Corporation
    Inventors: Atsumi Niwa, Yosuke Ueno, Shimon Teshima, Daijiro Anai, Yoshinobu Furusawa, Taishin Yoshida, Takahiro Uchimura, Eiji Hirata
  • Publication number: 20170201702
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Application
    Filed: May 21, 2015
    Publication date: July 13, 2017
    Inventors: Atsumi NIWA, Yosuke UENO, Shimon TESHIMA, Daijiro ANAI, Yoshinobu FURUSAWA, Taishin YOSHIDA, Takahiro UCHIMURA, Eiji HIRATA
  • Patent number: 9276565
    Abstract: A duty ratio correction circuit includes: a buffer circuit configured to generate a second signal based on a first signal, the second signal having a DC component corresponding to a first control signal; a waveform shaping section configured to shape a waveform of the second signal to generate a third signal that is a target of duty ratio correction; a first capacitor; and a first charge-discharge control circuit configured to selectively charge or discharge the first capacitor based on the third signal, to generate the first control signal.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: March 1, 2016
    Assignee: SONY CORPORATION
    Inventors: Kazutoshi Tomita, Shingo Harada, Atsumi Niwa
  • Publication number: 20150214932
    Abstract: A duty ratio correction circuit includes: a buffer circuit configured to generate a second signal based on a first signal, the second signal having a DC component corresponding to a first control signal; a waveform shaping section configured to shape a waveform of the second signal to generate a third signal that is a target of duty ratio correction; a first capacitor; and a first charge-discharge control circuit configured to selectively charge or discharge the first capacitor based on the third signal, to generate the first control signal.
    Type: Application
    Filed: December 11, 2014
    Publication date: July 30, 2015
    Inventors: Kazutoshi Tomita, Shingo Harada, Atsumi Niwa
  • Patent number: 8957805
    Abstract: A balanced signal processing circuit includes: a comparator; a first capacitor having a first end connected to a non-inverting input terminal of the comparator; a second capacitor having a first end connected to an inverting input terminal of the comparator; a first switch configured to apply a voltage signal to the first end of the first capacitor; a second switch configured to apply a voltage signal to the first end of the second capacitor; an operation state detection section configured to detect an operation state of the comparator; and an offset voltage correction section configured to apply a predetermined offset voltage to a second end of the first capacitor and a second end of the second capacitor when the operation state detection section detects an abnormal operation state of the comparator.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: February 17, 2015
    Assignee: Sony Corporation
    Inventor: Atsumi Niwa
  • Publication number: 20140253359
    Abstract: A balanced signal processing circuit includes: a comparator; a first capacitor having a first end connected to a non-inverting input terminal of the comparator; a second capacitor having a first end connected to an inverting input terminal of the comparator; a first switch configured to apply a voltage signal to the first end of the first capacitor; a second switch configured to apply a voltage signal to the first end of the second capacitor; an operation state detection section configured to detect an operation state of the comparator; and an offset voltage correction section configured to apply a predetermined offset voltage to a second end of the first capacitor and a second end of the second capacitor when the operation state detection section detects an abnormal operation state of the comparator.
    Type: Application
    Filed: February 25, 2014
    Publication date: September 11, 2014
    Applicant: Sony Corporation
    Inventor: Atsumi Niwa
  • Patent number: 8581763
    Abstract: A ?? modulator includes: a plurality of integrators cascaded to an input of an analog signal; a quantizer for quantizing an output signal of the integrator at a last stage and outputting a resultant digital signal; a DA converter for feedback for converting the digital signal obtained by the quantizer into an analog signal and supplying the analog signal to an input side of at least the integrator at a first stage; and an adder, arranged at an input stage side of the integrator at the last stage, for adding an output of the integrator at a preceding stage of the integrator at the last stage to at least one path signal supplied from at least another path via a first resistor having at least a first coefficient. The integrator at the last stage includes an operational amplifier, an integration capacitor, and a second resistor having a second coefficient.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: November 12, 2013
    Assignee: Sony Corporation
    Inventors: Atsumi Niwa, Yosuke Ueno
  • Patent number: 8466822
    Abstract: An AD conversion apparatus includes: a first AD converter for converting an input analog signal into a first digital signal; a second AD converter for converting an analog signal obtained as a result of multiplying the input analog signal by a coefficient ? into a second digital signal; a first computing unit for multiplying the first digital signal output by the first AD converter by ?2 obtained as a result of squaring the coefficient ?; a second computing unit for multiplying the second digital signal output by the second AD converter by ??1 which is the reciprocal of the coefficient ?; and a third computing unit for computing a difference between a first computation result output by the first computing unit and a second computation result output by the second computing unit and outputting the difference as a result of AD conversion carried out on the input analog signal.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: June 18, 2013
    Assignee: Sony Corporation
    Inventors: Atsumi Niwa, Yosuke Ueno
  • Publication number: 20120194371
    Abstract: An AD conversion apparatus includes: a first AD converter for converting an input analog signal into a first digital signal; a second AD converter for converting an analog signal obtained as a result of multiplying the input analog signal by a coefficient ? into a second digital signal; a first computing unit for multiplying the first digital signal output by the first AD converter by ?2 obtained as a result of squaring the coefficient ?; a second computing unit for multiplying the second digital signal output by the second AD converter by ??1 which is the reciprocal of the coefficient ?; and a third computing unit for computing a difference between a first computation result output by the first computing unit and a second computation result output by the second computing unit and outputting the difference as a result of AD conversion carried out on the input analog signal.
    Type: Application
    Filed: January 18, 2012
    Publication date: August 2, 2012
    Applicant: Sony Corporation
    Inventors: Atsumi Niwa, Yosuke Ueno
  • Publication number: 20120194365
    Abstract: A ??0 modulator includes: a plurality of integrators cascaded to an input of an analog signal; a quantizer for quantizing an output signal of the integrator at a last stage and outputting a resultant digital signal; a DA converter for feedback for converting the digital signal obtained by the quantizer into an analog signal and supplying the analog signal to an input side of at least the integrator at a first stage; and an adder, arranged at an input stage side of the integrator at the last stage, for adding an output of the integrator at a preceding stage of the integrator at the last stage to at least one path signal supplied from at least another path via a first resistor having at least a first coefficient. The integrator at the last stage includes an operational amplifier, an integration capacitor, and a second resistor having a second coefficient.
    Type: Application
    Filed: December 28, 2011
    Publication date: August 2, 2012
    Applicant: Sony Corporation
    Inventors: Atsumi Niwa, Yosuke Ueno
  • Patent number: 8077066
    Abstract: Disclosed herein is a ?? modulator including: at least one integrator; a quantizer for quantizing a signal output by the integrator and outputting the quantized signal as a digital signal; and a compensation section configured to compensate the ?? modulator for a non-ideal characteristic caused by an internal loop delay, wherein the compensation section is a feedback path formed to start at the output node of the quantizer and end at the input node of the integrator immediately preceding the quantizer, and the feedback path formed to start at the output node of the quantizer and end at the input node of the integrator realizes a frequency-independent part in combination with the integrator and an internal DA converter which adopts the NRZ technique to suppress the signal amplitude at the quantizer input.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: December 13, 2011
    Assignee: Sony Corporation
    Inventors: Atsumi Niwa, Tomohiro Matsumoto, Takashi Moue