Patents by Inventor Atsumi Yamaguchi

Atsumi Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040054981
    Abstract: In a method of forming a circuit pattern including fine pattern features and fine space, a hard mask layer is patterned with a first pattern defined by eliminating the fine space for merging the pattern features. Thereafter the hard mask layer is shrank. Next, the hard mask layer is patterned with a second pattern that is defined on the basis of the fine space. Finally, the circuit pattern is formed in an underlying layer using the hard mask layer as a mask.
    Type: Application
    Filed: February 10, 2003
    Publication date: March 18, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Takashi Okagawa, Tetsuya Yamada, Atsushi Ueno, Atsumi Yamaguchi, Kouichirou Tsujita
  • Publication number: 20040053908
    Abstract: Compounds represented by the following general formula: 1
    Type: Application
    Filed: April 18, 2003
    Publication date: March 18, 2004
    Inventors: Yasuhiro Funahashi, Akihiko Tsuruoka, Masayuki Matsukura, Toru Haneda, Yoshio Fukuda, Junichi Kamata, Keiko Takahashi, Tomohiro Matsushima, Kazuki Miyazaki, Ken-ichi Nomoto, Tatsuo Watanabe, Hiroshi Obaishi, Atsumi Yamaguchi, Sachi Suzuki, Katsuji Nakamura, Fusayo Mimura, Yuji Yamamoto, Junji Matsui, Kenji Matsui, Takako Yoshiba, Yasuyuki Suzuki, Itaru Arimoto
  • Publication number: 20030216018
    Abstract: The reduction of length of a gate electrode is suppressed in the process of thinning it. A hard mask (5a) is thinned and used to etch a gate electrode material film (4) to form a gate electrode. At this time, a resist mask (10) having an opening (11) over an active region (1) is formed; the resist mask (10) covers at least both ends in the length direction of the hard mask (5a) and exposes in the opening (11) at least the entirety of the part of the hard mask (5a) which lies right above the active region (1). The hard mask (5a) is thinned by etching using the resist mask (10) as a mask and therefore the hard mask (5a) is thinned in the part over the active region (1) without being shortened in the length direction. As a result, the gate electrode formed by using the thinned hard mask (5a) is not shortened in length.
    Type: Application
    Filed: November 21, 2002
    Publication date: November 20, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Tetsuya Yamada, Atsushi Ueno, Kouichirou Tsujita, Atsumi Yamaguchi, Takashi Okagawa
  • Patent number: 6607992
    Abstract: An antireflection coating has two-layer structure including lower and upper silicon nitride films (p-SiN films) formed by plasma CVD. For the lower p-SiN film, the real part of its complex index of refraction is set in the range not less than 1.9 nor more than 2.5, the imaginary part is set in the range of not less than 0.9 nor more than 1.7, and the film thickness is set in the range of not less than 20 nm nor more than 60 nm. For the upper p-SiN film, the real part of its complex index of refraction is set in the range not less than 1.7 nor more than 2.4, the imaginary part is set in the range of not less than 0.15 nor more than 0.75, and the film thickness is set in the range of not less than 10 nm nor more than 40 nm.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: August 19, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kouichirou Tsujita, Atsumi Yamaguchi, Junjiro Sakai, Kouji Oda, Koichiro Narimatsu
  • Publication number: 20030129509
    Abstract: A high-reliability evaluation technique is proposed which is related to semiconductor device manufacture. A photoresist formed on a wafer is subjected to exposure and development thereby to form a pair of opposed patterns (1, 2) with distance x in the photoresist, followed by measurement of distance x between the patterns (1, 2) in the photoresist. For example, the amount of variations in exposure energy is evaluated by using the measuring result. The evaluation is made by using distance x between patterns (1, 2) which are easy to change with variations in exposure energy, etc., thus improving the reliability of evaluation.
    Type: Application
    Filed: October 1, 2002
    Publication date: July 10, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Atsumi Yamaguchi
  • Publication number: 20030087196
    Abstract: A method can improve the etch resistance of a resist pattern and inhibit contraction due to SEM observations. A wafer substrate (1) with a predetermined resist pattern (2) formed thereon is immersed in a solution (10) of an organic substance (11), whereby the organic substance (11) in the solution (10) is introduced into holes (3) in the resist pattern (2). This improves the etch resistance of the resist pattern (2), since carbon generally contributes to improvements in the etch resistance of a resist film. The introduction of the organic substance (11) into the holes (3) can also inhibit contraction due to electron beam radiation involved in SEM observations.
    Type: Application
    Filed: August 13, 2002
    Publication date: May 8, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Kouichirou Tsujita, Atsumi Yamaguchi
  • Patent number: 6518196
    Abstract: The present invention provides a method of manufacturing a semiconductor device that reduces pitch dependence which represents a characteristic that the hole diameter decreases with increasing hole pitch. In the surface of a resist (1) where holes (5a-5e) having pitch dependence are formed, Ar+ ions of an inert gas are vertically implanted, for example, at an energy of 50 keV at a dose of 5.0×1015 cm−2. The ion implantation in the resist (1) shrinks the resist (1) and increases the hole diameters of the holes (5a-5e). At this time, since the hole diameters of the holes (5a-5d) of small hole pitches increase by a smaller amount than the hole diameter of the hole (5e) of a great hole pitch, the pitch dependence of the holes (5a-5e) can be reduced.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: February 11, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Yamada, Kouichirou Tsujita, Atsumi Yamaguchi
  • Publication number: 20020160619
    Abstract: The present invention provides a method of manufacturing a semiconductor device that reduces pitch dependence which represents a characteristic that the hole diameter decreases with increasing hole pitch. In the surface of a resist (1) where holes (5a-5e) having pitch dependence are formed, Ar+ ions of an inert gas are vertically implanted, for example, at an energy of 50 keV at a dose of 5.0×1015 cm−2. The ion implantation in the resist (1) shrinks the resist (1) and increases the hole diameters of the holes (5a-5e). At this time, since the hole diameters of the holes (5a-5d) of small hole pitches increase by a smaller amount than the hole diameter of the hole (5e) of a great hole pitch, the pitch dependence of the holes (5a-5e) can be reduced.
    Type: Application
    Filed: September 25, 2001
    Publication date: October 31, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Tetsuya Yamada, Kouichirou Tsujita, Atsumi Yamaguchi
  • Publication number: 20020123245
    Abstract: An antireflection coating has two-layer structure including lower and upper silicon nitride films (p-SiN films) formed by plasma CVD. For the lower p-SiN film, the real part of its complex index of refraction is set in the range not less than 1.9 nor more than 2.5, the imaginary part is set in the range of not less than 0.9 nor more than 1.7, and the film thickness is set in the range of not less than 20 nm nor more than 60 nm. For the upper p-SiN film, the real part of its complex index of refraction is set in the range not less than 1.7 nor more than 2.4, the imaginary part is set in the range of not less than 0.15 nor more than 0.75, and the film thickness is set in the range of not less than 10 nm nor more than 40 nm.
    Type: Application
    Filed: September 19, 2001
    Publication date: September 5, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Kouichirou Tsujita, Atsumi Yamaguchi, Junjiro Sakai, Kouji Oda, Koichiro Narimatsu
  • Publication number: 20020013055
    Abstract: Ions are implanted into a resist pattern for forming a wiring pattern. Argon is employed as the ion species, for performing ion implantation under 50 keV at 1×1016/cm2. Due to the ion implantation, the thickness of the resist pattern contracts to about 334 nm, i.e., about 75% of the thickness of 445 nm before ion implantation, while the composition of the resist pattern changes for improving resistance against etching for a silicon nitride film and a polysilicon layer. Thus obtained is a method of manufacturing a semiconductor device capable of suppressing critical dimension shift density difference (difference between a critical dimension shift on a rough region having a relatively large space width and that on a dense region having a relatively small space width).
    Type: Application
    Filed: July 27, 2001
    Publication date: January 31, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Atsumi Yamaguchi, Kouichirou Tsujita
  • Patent number: 6337175
    Abstract: An object is to enhance focus latitude and to suppress variations of widths due to different intervals in a resist pattern. A positive resist is applied on a substrate (1) and then a first exposure is performed to provide a resist pattern (2a) patterned into lines arranged at equal widths and equal intervals. Subsequently, a resin (6) containing an acid generator is applied on the substrate (1) to cover the resist pattern (2a). Next, a second exposure is performed with a photomask (5) to remove part of the resist pattern (2a).
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: January 8, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Atsumi Yamaguchi
  • Patent number: 6136479
    Abstract: A photomask where interconnection patterns and a contact hole pattern are drawn is used. According to the method, an overlay error due to a manufacturing error among reticles can be restricted.
    Type: Grant
    Filed: January 13, 1999
    Date of Patent: October 24, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Atsumi Yamaguchi
  • Patent number: 5981149
    Abstract: When a resist pattern used to manufacture a semiconductor integrated circuit element is formed, high alignment precision can be achieved.
    Type: Grant
    Filed: June 26, 1997
    Date of Patent: November 9, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Atsumi Yamaguchi
  • Patent number: 5952335
    Abstract: Novel fused polycyclic heterocycle derivatives having excellent antitumor effects and a process for producing the same. A compound represented by the following general formula (I) or pharmacologically acceptable salts thereof: ##STR1## wherein the ring A represents an optionally substituted monocyclic aromatic ring or a dicyclic fused ring in which at least one of the rings is an aromatic ring; the ring B represents pyrrole, 4H-1,4-oxazine, 4H-1,4-thiazine or 4(1H)-pyridone; the ring C represents an optionally substituted, monocyclic or dicyclic fused aromatic ring; and Y represents a group represented by the formula --e--f (wherein e represents a lower alkylene; and f represents amidino, guanidino or amino optionally substituted by optionally hydroxylated or optionally lower-alkylaminated lower alkyl;provided that the cases where the rings A and B are both optionally substituted monocyclic aromatic rings are excluded. Which has an excellent antitumor activity.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: September 14, 1999
    Assignee: Eisai Co., Ltd.
    Inventors: Hiroyuki Sugumi, Jun Niijima, Yoshihiko Kotake, Toshimi Okada, Jun-ichi Kamata, Kentaro Yoshimatsu, Takeshi Nagasu, Katsuji Nakamura, Toshimitsu Uenaka, Atsumi Yamaguchi, Hiroshi Yoshino, Nozomu Koyanagi, Kyosuke Kito
  • Patent number: 5902718
    Abstract: Methods for developing a positive photoresist comprise providing a positive photoresist and developing the positive photoresist with a developer comprising a quaternary ammonium hydroxide and a quaternary ammonium halogenide. The positive photoresist has an unexposed portion dissolution rate with a 2.38 weight % aqueous solution of tetramethyl ammonium hydroxide of about 1 .ANG./sec or less. The quaternary ammonium halogenide is of the formula ##STR1## wherein R.sub.1, R.sub.2, R.sub.3, R.sub.4 are selected from the group consisting of ethyl, methyl, hydroxy methyl, hydroxy ethyl and hydrogen, and X is a halogen atom.
    Type: Grant
    Filed: June 1, 1992
    Date of Patent: May 11, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Atsumi Yamaguchi