Abstract: A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.

Abstract: A semiconductor device of the present invention comprises a first step-down voltage circuit to generate a first step-down voltage lower than an externally-supplied power supply voltage, and a second step-down voltage circuit to generate a second step-down voltage lower than the first step-down voltage. The first step-down voltage circuit has a withstand voltage no lower than the power supply voltage and the second step-down voltage circuit has a withstand voltage no lower than the first step-down voltage.

Abstract: A step-down circuit is connected between a power supply node for supplying a supply voltage and an internal power supply line for supplying a power to the object circuit and steps-down the supply voltage, and supplies the stepped-down voltage to the object circuit through the internal power supply line. The step-down circuit includes a comparison circuit that compares a reference voltage with the voltage of the internal power supply line, and a driver that adjusts a current flowing between the internal power supply line and the power supply node according to the comparison result of the comparison circuit. The activity level of the driver is controlled so as to rise in a predetermined rising period synchronously with an activated operation of the object circuit and to fall in a predetermined falling period that comes after the rising period.

Abstract: A semiconductor storage device includes a timing allocation unit that sets refresh timing to preferentially perform a refresh operation for maintaining data and data access timing to preferentially perform a data access operation for reading or writing the data in accordance with a clock signal with respect to each memory bank including a plurality of memory cells, and a waiting unit that waits start of the data access operation until the data access timing is started in a case where a request for the data access operation is made during the refresh timing and waits start of the refresh operation until the refresh timing is started in a case where a request for the refresh operation is made during the data access timing.

Abstract: A write amplifier power generating circuit includes a control unit for changing an output voltage. In a first write cycle in which a pair of bit lines are being amplified, a write operation is performed by an overdrive write method in which a high level from a write amplifier is set to a first voltage (for example, a power supply voltage). In a second write cycle after amplification in the pair of the bit lines has been completed, a write operation is performed by a write method in which the high level from the write amplifier is set to a second voltage (for example, an internal voltage).

Abstract: A step-down circuit is connected between a power supply node for supplying a supply voltage and an internal power supply line for supplying a power to the object circuit and steps-down the supply voltage, and supplies the stepped-down voltage to the object circuit through the internal power supply line. The step-down circuit includes a comparison circuit that compares a reference voltage with the voltage of the internal power supply line, and a driver that adjusts a current flowing between the internal power supply line and the power supply node according to the comparison result of the comparison circuit. The activity level of the driver is controlled so as to rise in a predetermined rising period synchronously with an activated operation of the object circuit and to fall in a predetermined falling period that comes after the rising period.

Abstract: A write amplifier power generating circuit includes a control unit for changing an output voltage. In a first write cycle in which a pair of bit lines are being amplified, a write operation is performed by an overdrive write method in which a high level from a write amplifier is set to a first voltage (for example, a power supply voltage). In a second write cycle after amplification in the pair of the bit lines has been completed, a write operation is performed by a write method in which the high level from the write amplifier is set to a second voltage (for example, an internal voltage).

Abstract: A delay circuit has a circuit structure dominated by an NMOS or a PMOS transistor. The delay circuit is supplied with, as a power supply voltage, an output voltage of a power supply voltage step-down circuit having a level generating circuit for generating a reference voltage obtained by an offset voltage and a manufacturing variation dependent voltage, and an m-time voltage generating circuit. A semiconductor device includes the delay circuit.

Abstract: An internal power supply generating circuit has a control circuit for controlling a control node voltage of a driver circuit thereof. During an overdrive duration, the control node voltage is set at an appropriate level of an operation range by controlling the control node voltage by the control circuit. By setting the control node voltage at the appropriate level, the internal power supply generating circuit can supply an internal power-supply voltage without a dead band after the overdrive duration. With this structure, the internal power supply generating circuit without the dead band can be obtained and a semiconductor device operable at a high speed comprising the internal power supply generating circuit can be obtained.

Abstract: A semiconductor device of the present invention comprises a first step-down voltage circuit to generate a first step-down voltage lower than an externally-supplied power supply voltage, and a second step-down voltage circuit to generate a second step-down voltage lower than the first step-down voltage. The first step-down voltage circuit has a withstand voltage no lower than the power supply voltage and the second step-down voltage circuit has a withstand voltage no lower than the first step-down voltage.

Abstract: An overdrive period control device includes a pre-charge circuit connected to a node on which a potential is detected and for raising a potential at the node to a first potential; a delay element one terminal of which is connected to the node; a charge circuit supplying a power source voltage to the other terminal of the delay element at the input timing of a signal from the outside and raising the potential at the node to the power source voltage; and a comparison circuit comparing the potential at the node with a reference potential and detecting the timing at which both levels of the potentials coincide. The device outputs a signal indicating a period determined by the input timing of the signal from the outside and the timing in which the comparison circuit detects that the levels coincide.

Abstract: An internal power supply generating circuit has a control circuit for controlling a control node voltage of a driver circuit thereof. During an overdrive duration, the control node voltage is set at an appropriate level of an operation range by controlling the control node voltage by the control circuit. By setting the control node voltage at the appropriate level, the internal power supply generating circuit can supply an internal power-supply voltage without a dead band after the overdrive duration. With this structure, the internal power supply generating circuit without the dead band can be obtained and a semiconductor device operable at a high speed comprising the internal power supply generating circuit can be obtained.

Abstract: Disclosed is an apparatus for detecting power supply dependency and process dependency of a delay circuit to enable control of the delay of the delay circuit and operation acceleration/deceleration. The apparatus includes a first delay circuit receiving a first signal and delaying the first signal received by a preset delay time to output the so delayed signal, a second delay circuit receiving the first signal in common with the first delay circuit and outputting signals of different delay amounts from plural output ends thereof, and a plural number of comparator circuits provided in association with the plural outputs of the second delay circuit, each configured to receive an output of the first delay circuit and a corresponding output of the second delay circuit and to compare the signals received. The delay of the control signal is varied by a variable delay circuit, based on plural outputs of the plural comparator circuits, in order to variably control e.g.

Abstract: An overdrive period control device includes a pre-charge circuit connected to a node on which a potential is detected and for raising a potential at the node to a first potential; a delay element one terminal of which is connected to the node; a charge circuit supplying a power source voltage to the other terminal of the delay element at the input timing of a signal from the outside and raising the potential at the node to the power source voltage; and a comparison circuit comparing the potential at the node with a reference potential and detecting the timing at which both levels of the potentials coincide. The device outputs a signal indicating a period determined by the input timing of the signal from the outside and the timing in which the comparison circuit detects that the levels coincide.

Abstract: A delay circuit has a circuit structure dominated by an NMOS or a PMOS transistor. The delay circuit is supplied with, as a power supply voltage, an output voltage of a power supply voltage step-down circuit having a level generating circuit for generating a reference voltage obtained by an offset voltage and a manufacturing variation dependent voltage, and an m-time voltage generating circuit. A semiconductor device includes the delay circuit.

Abstract: An output buffer circuit (300) having an output time which may be reduced is provided. The output buffer circuit (300) can include a selector (1), a precharge circuit (2) and a buffer (3). Selector (1) can be responsive to a control signal (SELB) and may provide data on a data signal line (9). Precharge circuit (2) may be responsive to control signal (SELB) and may precharge data signal line (9) to a first potential when control signal is in a disable state. Selector (1) may electrically disconnect data input terminals (4 and 5) from data signal line (9) when control signal (SELB) is in the disable state. Buffer (3) may output a logic value from the data signal line (9) when control signal (SELB) is in an enable state.

Abstract: An output buffer circuit (300) having an output time which may be reduced is provided. The output buffer circuit (300) can include a selector (1), a precharge circuit (2) and a buffer (3). Selector (1) can be responsive to a control signal (SELB) and may provide data on a data signal line (9). Precharge circuit (2) may be responsive to control signal (SELB) and may precharge data signal line (9) to a first potential when control signal is in a disable state. Selector (1) may electrically disconnect data input terminals (4 and 5) from data signal line (9) when control signal (SELB) is in the disable state. Buffer (3) may output a logic value from the data signal line (9) when control signal (SELB) is in an enable state.

Abstract: A semiconductor storage unit to be disclosed includes a bank block (231) having banks (251) and (252) with memory cell arrays (311) and (312), global I/O lines (261) and (262), I/O amplifier (281) and (282) and column decoder groups (351) and (352); and a bank selective circuit (291) provided in common with the bank blocks (251) and (252) that produces a column select signal YS0 or YS1 for activating the corresponding column decoder on the basis of bank select signals BS0 to BS2 and /BS0 to /BS2 and a column multi-select delay signal YMD0 for activating the corresponding I/O amplifier (281) or (282). Thereby, it is possible to reduce the number of wiring lines in a semiconductor storage unit with a plurality of banks and to normally perform a test such as fault analysis or the like.

Abstract: A semiconductor memory device which enables holding of two or more addresses and selecting of an address output corresponding to kinds of commands with a sufficient operational margin. The semiconductor memory device of the present invention is so configured that a command decoder generates a first controlling signal after a first period following the inputting of a read command, a second controlling signal after a second period following the inputting of a write command, and an operation instructing signal to be fed to a column control circuit in response to first and second controlling signals, and a burst counter makes an input address delayed by first and second periods and outputs the address delayed by the first period as a read address in response to a first controlling signal and the address delayed by the second period as a write address in response to a second controlling signal.