Abstract: A semiconductor memory device operates in synchronization with a system clock, without using a synchronous circuit such as a DLL or a PLL. The semiconductor memory device includes a synchronous circuit for generating output signals phase aligned with the system clock, a synchronous circuit selection circuit that performs switching between a synchronous circuit selection mode and a synchronous circuit non-selection mode, and a reference edge specifying register that specifies an edge of an internal clock which serves as a reference for outputting read data in the synchronous circuit non-selection mode. In the synchronous circuit selection mode, the read data is output by adjusting a phase deviation of the internal clock with respect to the system clock, using the synchronous circuit. In the synchronous circuit non-selection mode, the read data is output in synchronization with the internal clock, without using the synchronous circuit.

Abstract: A memory system includes a plurality of semiconductor memory devices each including a termination resistance circuit that can be controlled to be turned on or off from an outside by a termination resistance control signal, and a memory controller. The memory controller includes a termination resistance control unit that outputs the termination resistance control signal so that when a read command or a write command is executed on one of the semiconductor memory devices, termination resistances of all of the semiconductor memory devices are turned on, and when any of the semiconductor memory devices does not execute the read command or the write command, the termination resistances of all of the semiconductor memory devices are turned off. The termination resistance circuit of one of the semiconductor memory devices is turned off, irrespective of the level of the termination resistance control signal when the one of the semiconductor memory devices outputs data in response to the read command.

Abstract: A semiconductor memory device has an operation mode in which a read/write operation is performed in response to a command supplied externally in synchronization with a clock, and a power-down mode in which no external read/write command is accepted. The semiconductor memory device performs a refresh operation in response to an externally supplied signal during the power-down mode. A memory system has a plurality of the semiconductor devices and a memory controller. The memory controller outputs a control signal during the power-down mode, and the plurality of semiconductor devices perform a refresh operation in response to the control signal during the power-down mode.

Abstract: According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory 200 is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.

Abstract: According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory 200 is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.

Abstract: A semiconductor integrated circuit includes a temperature detecting unit that detects the temperature of a chip, and an A/D converter that converts an analog output VBE from the temperature detecting unit into a digital output. The A/D converter includes an up/down counter, a D/A converter that converts an output T2 from the up/down counter into an analog output, and a comparator that compares the analog output DAC_OUT of the D/A converter and the analog output VBE (VTEMP) of the temperature detecting unit. The up/down counter is adapted to be able to preset an initial value that is different from the minimum value or the maximum value. Accordingly, the determination time required at the initial conversion can be reduced although the linear search method is used.

Abstract: According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory 200 is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.

Abstract: In an addressing unit fort reducing a wasteful time created to reach an address latch to attain fast processing, a pre-decoder for pre-decoding an X address and a Y address is provided in a preceding stage to the address latch, the address signal pre-decoded by the pre-docoder is latched in the address latch and the latched address signal is decoded by a decoder. Thus, the pre-docode process can be conducted in the same time period required to latch the address signal in a conventional unit in which the pre-decoder is arranged in a succeeding stage of the address latch circuit, and after the address latching, only the decode process is needed.

Abstract: In an addressing unit fort reducing a wasteful time created to reach an address latch to attain fast processing, a pre-decoder for pre-decoding an X address and a Y address is provided in a preceding stage to the address latch, the address signal pre-decoded by the pre-decoder is latched in the address latch and the latched address signal is decoded by a decoder. Thus, the pre-decode process can be conducted in the same time period required to latch the address signal in a conventional unit in which the pre-decoder is arranged in a succeeding stage of the address latch circuit, and after the address latching, only the decode process is needed.

Abstract: A semiconductor memory includes a plurality of semiconductor memory cells and a first select line for providing a first select signal to access a selected memory cell, a second select line for providing a second select signal to access a selected memory cell, the first and second select signals being independent, a first transmission line for coupling an information with the memory cell synchronizing to the first signal and a second transmission line for coupling an information with the memory cell synchronizing to the second signal. Each memory cell includes a storage element for storing an information, with at least one input-output terminal and at least one input-output section.

Abstract: A latch up phenomenon is prevented by forming an insulating film on a semiconductor substrate, allowing a semiconductor layer to extend from both end portions of an opening provided in the insulating film on the semiconductor substrate onto the insulating film, forming a channel region within the opening, and utilizing semiconductor layers on the insulating film as a source and a drain. Further, in the semiconductor layer extending from the semiconductor substrate onto the insulating film, when the portion in contact with the semiconductor substrate is formed as a part of the inversion layer (channel), the width of the channel portion which utilizes the semiconductor substrate can be reduced, which enables a high-density integration to be realized.

Abstract: Method and apparatus for writing and reading data into/from a first-in-first-out (FIFO) memory having memory areas arranged in a matrix are disclosed in which data of a series of first words each represented by a predetermined first number of bits are stored such that the first words are sequentially stored in selected memory areas of the memory and the stored data is read out of the memory such that the stored words are read out as a series of second words each represented by a predetermined second number, different from said first number, of bits, and in the same order as that in which the words have been stored.

Abstract: A bipolar-complementary metal oxide semiconductor (Bi-CMOS) inverter includes a CMOS inverter, an npn-type bipolar transistor, and an n-channel MOS transistor. An emitter of an n-channel MOS transistor of the CMOS inverter is connected to an emitter of the bipolar transistor and a drain of the MOS transistor. A gate of the MOS transistor is connected to an input of the CMOS inverter. When an input voltage applied to the CMOS inverter is switched to a high level, charges at an output of the CMOS inverter and at the emitter of the bipolar transistor are pulled out. During this time, the voltage at the output of the CMOS inverter decreases so as to follow the decrease of the voltage at the emitter of the bipolar transistor.