Patents by Inventor Atsuro Inada

Atsuro Inada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8492227
    Abstract: An etching stopper film is formed over a first insulating film. Then, a second insulating film is formed with a thickness that allows concave and convex portions formed due to a first gate electrode to remain. Then, anisotropic etching is performed using the etching stopper film as a stopper to remove the second insulating film over a second gate electrode and form a first side wall spacer of the first gate electrode. Then, the etching stopper film is removed. Then, anisotropic etching is performed on the first insulating film to form a second side wall spacer over the second gate electrode and form a third side wall spacer which is disposed inside the first side wall spacer over the first gate electrode.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: July 23, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Akira Mitsuiki, Atsuro Inada
  • Patent number: 8123901
    Abstract: The wafer processing apparatus 100 included in an etching apparatus selectively etches the peripheral portion of a wafer 200. The wafer processing apparatus 100 includes a lower electrode 112 as a stage on which the wafer 200 is placed, a process gas introducing duct 120 supplying therethgouh a process gas etching the peripheral portion, an etching-interfering gas introducing duct 118 supplying therethrough an etching-interfering gas interfering supply of the process gas to the center portion of the wafer, and a movable alignment mechanism 102 aligning the wafer on the lower electrode 112. The etching-interfering gas introducing duct 118 and the process gas introducing duct 120 can be provided in an upper electrode 106.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: February 28, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Atsuro Inada, Kazuhiko Ueno
  • Publication number: 20110053367
    Abstract: An etching stopper film is formed over a first insulating film. Then, a second insulating film is formed with a thickness that allows concave and convex portions formed due to a first gate electrode to remain. Then, anisotropic etching is performed using the etching stopper film as a stopper to remove the second insulating film over a second gate electrode and form a first side wall spacer of the first gate electrode. Then, the etching stopper film is removed. Then, anisotropic etching is performed on the first insulating film to form a second side wall spacer over the second gate electrode and form a third side wall spacer which is disposed inside the first side wall spacer over the first gate electrode.
    Type: Application
    Filed: July 16, 2010
    Publication date: March 3, 2011
    Inventors: Akira MITSUIKI, Atsuro Inada
  • Publication number: 20080194107
    Abstract: The present invention aims to improve the controllability of dimensions at the time when a silicon substrate or a film formed on top of the silicon substrate is etched. For this purpose, a SiN film is formed so as to be in contact with the top of an element-forming surface of a silicon substrate, and the SiN film is selectively removed to form an opening portion. Then, a plasma processing is carried out on the element-forming surface of the silicon substrate to remove deposits attached on sidewalls of the opening portion formed in the SiN film. After that, the silicon substrate is selectively removed by using the SiN film as a mask to form a concave portion in the silicon substrate.
    Type: Application
    Filed: February 5, 2008
    Publication date: August 14, 2008
    Applicant: NEC Electronics Corporation
    Inventors: Akira Mitsuiki, Atsuro Inada
  • Publication number: 20060086462
    Abstract: The wafer processing apparatus 100 included in an etching apparatus selectively etches the peripheral portion of a wafer 200. The wafer processing apparatus 100 includes a lower electrode 112 as a stage on which the wafer 200 is placed, a process gas introducing duct 120 supplying therethgouh a process gas etching the peripheral portion, an etching-interfering gas introducing duct 118 supplying therethrough an etching-interfering gas interfering supply of the process gas to the center portion of the wafer, and a movable alignment mechanism 102 aligning the wafer on the lower electrode 112. The etching-interfering gas introducing duct 118 and the process gas introducing duct 120 can be provided in an upper electrode 106.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 27, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Atsuro Inada, Kazuhiko Ueno
  • Publication number: 20060086461
    Abstract: A wafer processing apparatus 100 involved in an etching apparatus takes part in selective etching of the peripheral portion of a wafer 200. The wafer processing apparatus 100 includes a lower electrode 112 which is a stage on which the wafer 200 is placed, a process gas introducing duct 120 supplying a process gas etching the peripheral portion, and a plurality of etching-interfering gas introducing ducts 118a, 118b, 118c and 118d supplying etching-interfering gas an interfering supply of the process gas to the center of the wafer 200. The etching-interfering gas coming through the plurality of etching-interfering gas introducing ducts 118a to 118d is supplied in a plurality of directions, while being independently controlled in each supply volume.
    Type: Application
    Filed: October 19, 2005
    Publication date: April 27, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Atsuro Inada, Kazuhiko Ueno