Abstract: A hollow bar is provided in a bathroom and connected with a faucet 10 and a showerhead 1. The hollow bar comprises a slide bar 3 for the hook 2 of the showerhead or a grip bar 15 for a user. Water treating material such as a filter medium, ion exchange resin and ceramics is placed in the hollow bar and water jetted from the faucet 10 passes the water treating material in the hollow bar. The water is treated by the water treating material and the treated water is guided to and dispensed from the showerhead.

Abstract: A scale indication apparatus and a flow meter having the scale indication apparatus, which improve the usability and the versatility. The scale indication apparatus (31) is rotatably attached to a measurement apparatus (1) which can not be externally operated and indicates a scale when reading the displacement magnitude of an indicator (19) of the measurement apparatus (1). A scale indication position can be sequentially moved to reset the displacement magnitude of the indicator (19) by the rotating operation in a first direction without movement in an axial direction, and the scale indication apparatus (31) can be moved in the axial direction to be detached from the measurement apparatus (1) by the rotating operation in a second direction opposite from the first direction.

Abstract: Red, green and blue light beams from a light source portion travel via a first optical system and enter a reflecting surface of a rotating polygon mirror at different angles so as not to overlap each other. The rotating polygon mirror makes these light beams perform scanning when reflecting these light beams. The light beams for the scanning enter a second optical system at different angles and are led to different positions on an image display panel. The second optical system forms an image that is rotated by 90° from that on the rotating polygon mirror on the image display panel. On the image display panel, belt-like regions illuminated by the light beams of individual colors are formed in parallel with each other, and these illuminated regions are moved continuously by the scanning. Each pixel of the image display panel is driven by a signal corresponding to a color of light entering this pixel. A formed color image is magnified and projected by a projection optical system.

Abstract: A dynamic memory device having a plurality of bit line pairs, a plurality of word lines, and a plurality of memory cells disposed at intersections thereof. The dynamic memory device includes a data bus and sense amplifiers. The data bus is connected a write amplifier. The sense amplifiers are provided to each of the bit line pairs, for amplifying voltage between the bit line pairs. In a stress testing mode, a plurality of the bit line pairs are commonly connected to the data bus, the write amplifier applies high and low voltages to the simultaneously connected bit line pairs, and thereafter the sense amplifiers associated with the selected bit line pairs are activated.

Abstract: An image display apparatus is provided for enlarging and projecting a light emitted from a plurality of self-emitting elements on a screen by beam scanning means, which is an image display apparatus having little or no luminance unevenness by solving the conventional problem of causing luminance unevenness in images projected on the screen due to a variance in luminance characteristics of each self-emitting element. It is configured such that a part of the light scanned on the screen from the beam scanning means is provided to a photodetector element that converts the intensity of the light into an electric signal so as to correct a driving signal to be supplied to the self-emitting element by the intensity of the light detected by this photodetector element.

Abstract: A transistor of a driver in the semiconductor integrated circuit according to the present invention has its gate connected to a controlling circuit, and has its drain connected to a sense amplifier. The controlling circuit supplies the gate of the transistor with a gate-to-source voltage exceeding or below other power supply voltages. The drain-to-source resistance of the transistor in the on state becomes sufficiently lower as compared with that in the case of supplying the power supply voltages between the gate and source of the transistor. Accordingly, the amplifying speed of the sense amplifier is heightened without altering the sense amplifier and the driver. Besides, the amplifying speed of the sense amplifier is heightened without raising the power supply voltage which supplies the carriers to the driver.

Abstract: A memory device having memory cells at cross sections of word lines and bit lines, a word-line driver for driving the word lines in response to a first activation signal, a delay circuit for generating a second activation signal that delays the first activation signal, and a sense amp for amplifying the voltage read from the memory cell in response to the second activation signal, comprises: a first power-supply voltage that is supplied to the word-line driver, and a second power-supply voltage that is supplied to the delay circuit, where the second power-supply voltage is generated from the first power-supply voltage. In the present invention, there is a first power-supply voltage that is supplied to the word-line driver, and a second power-supply voltage that is supplied to the delay circuit.

Abstract: A multi-lingual information retrieval system which includes an information storage section for storing information, a data storage section for storing data for language conversion and for converting the stored information to strings of characters in natural language expressions in order to enable a person's interpretation, an interface section for user's interaction operations for information retrieval, a retrieval section for retrieving information from the information storage section in response to a request for a retrieval from the interface section, and an output section for outputting a retrieved result of the retrieval section. The data storage section coexistently stores the information therein in a plurality of different languages, thereby making possible to retrieve identical information by use of the plurality of different languages.

Abstract: A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle-time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

Abstract: A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state.

Abstract: A method for making document information searches. In performing a document search with respect to the desired key word, two stages of presearch are carried out. In a first stage of presearch, a character component table in which an existence of character codes for every document is stated with respect to all the character codes contained in the group of document text data of stored documents is generated, and the character component table is searched for all the character strings constituting a desiredly designated search subject key word to thereby extract all the documents each containing all the character codes constituting the search subject key word. In a second stage of presearch, contracted text data for every document in which adjuncts and duplication of repeatedly stated words contained in advance in the text data are eliminated is generated, and the documents each containing the search subject key words by word are extracted from the documents extracted by the first presearch.

Abstract: A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip, for data transfer with an adjacent memory chip, second input/output nodes, provided for the at least one memory chip, for data transfer with an adjacent logic chip, and a package housing the at least one logic chip and the at least one memory chip, wherein the first input/output nodes are arranged along the one side of the at least one logic chip, and the second input/output nodes are arranged along the one side of the at least one memory chip.

Abstract: A light source for emitting a white light in one direction, color light separating means for separating the white light from the light source into three color lights of red light, blue light and green light, modulating means including liquid crystal light valves for modulating the polarized lights contained in the luminous fluxes from the color light separating means, and producing a video image, color light combining means for combining the modulated luminous fluxes after being modulated by the modulating means, and projection optical means for projecting the combined luminous flux obtained by the color light combining means on a screen. A polarizer is disposed at the light exit side of the modulating means.

Abstract: A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state.

Abstract: A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

Abstract: A text data registering and retrieving method capable of improving the transaction processing performance is provided. The document number of a document for which deletion or replacement has been newly requested is registered in an updated document number list. The text data of the document for which insertion or replacement has been newly requested is registered in an update text buffer. The text data stored temporarily in the update text buffer is registered in a plural-character occurrence file defining a text index in a character component file merge step. The data registered in the plural-character occurrence file is retrieved for query terms. The text data stored in the update text buffer is retrieved for the query terms. The document number of a document updated or deleted is deleted from the result of retrieval in the plural-character occurrence file. Also, the result or the document number obtained in the, update text buffer is added to the result of retrieval to provide a final retrieval result.

Abstract: A semiconductor integrated circuit having a DRAM, or the like, includes a memory cell block containing a plurality of memory cells, and a core circuit portion for selecting and activating a specified memory cell inside the memory cell block, and is constituted so that a step-up voltage is applied to the core circuit portion at the time of an activated state. The semiconductor integrated circuit further includes a step-up voltage lowering unit for lowering the step-up voltage by a predetermined value and a unit for selectively supplying the step-up voltage and an output voltage of the step-up voltage lowering unit to the core circuit portion.

Abstract: A semiconductor memory device uses a wave pipeline system which can reduce a power consumption by reducing a current for charging a data bus between a memory core part and an output circuit. A single line data bus transmits read data output from the memory core part. A data bus drive circuit outputs the read read data to send to the single data bus. Each of a plurality of data latch circuits has a data input terminal connected to the data bus. A data input control circuit inputs the read data which is serially transmitted on the data bus to the data latch circuits in parallel in response to an operation of the data bus drive circuit. A data output control circuit outputs the latched read data in an order of latching by sequentially selecting outputs of the data latch circuits.

Abstract: A structure of a redundant cell array applicable for a compression test in which a defective cell is detected by concurrently selecting cells in a plurality of segments is provided. In the structure of the redundant cell array in a semiconductor storage device according to the present invention, areas for the compression test in which data write and read are performed by concurrently selecting memory cells in a plurality of segments SGM can be replaced to a redundancy cell array 30. That is, at least, one part of addresses Y0 and Y1 decoded by a column decoder 40 is stored in a redundant ROM of a redundancy detector 34 and is replaced to the redundant cell array 30 when the addresses coincide with the stored address. In this case, at least, one part of the addresses Y2 and Y3 decoded by a segment decoder 50 is supplied to a redundant column decoder 36 provided for the redundant cell array 30.

Abstract: A semiconductor or memory device has a decoder circuit for decoding a plurality of external address signals. The external address signals include first and second external address signals. A first address buffer receives the first external address signals and outputs first internal address signals to first address lines. A second address buffer receives the second external address signals and outputs second internal address signals to second address lines. First predecoders have input terminals connected to the first address lines, and output first predecode signals to first predecode lines. Second predecoders have input terminals connected to the second address lines and output second predecode signals to second predecode lines. Main decoders have input terminals connected to the first predecode lines and the second predecode lines and output decode signals. The number of the first external address signals are greater than the number of the second external address signals.