Patents by Inventor Atsushi Himeno
Atsushi Himeno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240060824Abstract: An infrared sensor according to the present disclosure includes a transistor, a cavity layer, and a sensor layer. The cavity layer includes a cavity. The sensor layer includes a phononic crystal in which holes are arranged. In plan view, the infrared sensor includes a first region and a second region. The first region includes a transistor. The second region includes the cavity. The cavity layer includes a flat major surface. The major surface is disposed around the cavity, and extends across both the first region and the second region. The sensor layer is disposed on the major surface.Type: ApplicationFiled: October 27, 2023Publication date: February 22, 2024Inventors: KOUHEI TAKAHASHI, MASAKI FUJIKANE, KUNIHIKO NAKAMURA, ATSUSHI HIMENO, NAOKI TAMBO, YUKI NAKATA, HIROYUKI TANAKA
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Patent number: 11889776Abstract: A variable resistance non-volatile memory element includes first and second electrodes and a variable resistance layer between the electrodes. The layer has a resistance value reversibly variable based on an electrical signal. The layer includes a first variable resistance layer that includes an oxygen deficient first metal oxide containing a first metal element and oxygen, and a second variable resistance layer that includes a composite oxide containing the first metal element, a second metal element different from the first metal element, and oxygen, and having a different degree of oxygen deficiency from the first metal oxide. The composite oxide has a lower degree of oxygen deficiency than the first metal oxide. At room temperature, the composite oxide has a smaller oxygen diffusion coefficient than a second metal oxide containing the first metal element and oxygen, and having the degree of oxygen deficiency equal to that of the composite oxide.Type: GrantFiled: June 23, 2021Date of Patent: January 30, 2024Assignee: Nuvoton Technology Corporation JapanInventors: Ryutaro Yasuhara, Satoru Fujii, Takumi Mikawa, Atsushi Himeno, Kengo Nishio, Takehide Miyazaki, Hiroyuki Akinaga, Yasuhisa Naitoh, Hisashi Shima
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Publication number: 20210408119Abstract: In a non-volatile storage device, a first lower-layer metal wire, a lower plug, a variable resistance element, an upper plug, and a first upper-layer metal wire are formed in that order from below in a storage region, and a second lower-layer metal wire, a first via, a middle-layer metal wire, a second via, and a second upper-layer metal wire are formed in that order from below in a circuit region. The first and second lower-layer metal wires are formed in the same layer, and the first and second upper-layer metal wires are formed on the same layer. Relative to a substrate, the variable resistance element and the middle-layer metal wire have top faces at different heights, bottom faces at different heights, or both top faces and bottom faces at different heights.Type: ApplicationFiled: August 27, 2021Publication date: December 30, 2021Inventors: Atsushi HIMENO, Yukio HAYAKAWA, Koichi KAWASHIMA, Ryutaro YASUHARA
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Publication number: 20210320248Abstract: A variable resistance non-volatile memory element includes first and second electrodes and a variable resistance layer between the electrodes. The layer has a resistance value reversibly variable based on an electrical signal. The layer includes a first variable resistance layer that includes an oxygen deficient first metal oxide containing a first metal element and oxygen, and a second variable resistance layer that includes a composite oxide containing the first metal element, a second metal element different from the first metal element, and oxygen, and having a different degree of oxygen deficiency from the first metal oxide. The composite oxide has a lower degree of oxygen deficiency than the first metal oxide. At room temperature, the composite oxide has a smaller oxygen diffusion coefficient than a second metal oxide containing the first metal element and oxygen, and having the degree of oxygen deficiency equal to that of the composite oxide.Type: ApplicationFiled: June 23, 2021Publication date: October 14, 2021Inventors: Ryutaro YASUHARA, Satoru FUJII, Takumi MIKAWA, Atsushi HIMENO, Kengo NISHIO, Takehide MIYAZAKI, Hiroyuki AKINAGA, Yasuhisa NAITOH, Hisashi SHIMA
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Patent number: 9680093Abstract: A nonvolatile memory element including: a first electrode; a second electrode; a variable resistance layer that is between the first electrode and the second electrode and includes, as stacked layers, a first variable resistance layer connected to the first electrode and a second variable resistance layer connected to the second electrode; and a side wall protecting layer that has oxygen barrier properties and covers a side surface of the variable resistance layer. The first variable resistance layer includes a first metal oxide and a third metal oxide formed around the first metal oxide and having an oxygen deficiency lower than that of the first metal oxide, and the second variable resistance layer includes a second metal oxide having an oxygen deficiency lower than that of the first metal oxide.Type: GrantFiled: September 10, 2012Date of Patent: June 13, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Shinichi Yoneda, Takumi Mikawa, Satoru Ito, Yukio Hayakawa, Atsushi Himeno
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Patent number: 9478584Abstract: A nonvolatile memory device includes an insulating layer, oxygen diffusion prevention layers disposed on the insulating layer, a plurality of contact plugs, each of the plurality of the contact plugs penetrating through each of the plurality of the oxygen diffusion prevention layers and at least a part of the insulating layer, and a plurality of resistance-variable elements, each of the plurality of the resistance-variable elements covering each of the plurality of the contact plugs exposed on surfaces of the oxygen diffusion prevention layers and being electrically connected to each of the plurality of the contact plugs Each of the oxygen diffusion prevention layers is provided only between the insulating layer and each of the plurality of the resistance-variable elements to correspond to each of the plurality of the contact plugs arranged for each of the plurality of the resistance-variable elements.Type: GrantFiled: December 3, 2014Date of Patent: October 25, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yoshio Kawashima, Yukio Hayakawa, Atsushi Himeno
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Patent number: 9214628Abstract: A nonvolatile memory element according to the present invention includes a first metal line; a plug formed on the first metal line and connected to the first metal line; a stacked structure including a first electrode, a second electrode, and a variable resistance layer, the stacked structure being formed on a plug which is connected to the first electrode; a second metal line formed on the stacked structure and directly connected to the second electrode; and a side wall protective layer which covers the side wall of the stacked structure and has an insulating property and an oxygen barrier property, wherein part of a lower surface of the second metal line is located under an upper surface of the stacked structure.Type: GrantFiled: November 30, 2011Date of Patent: December 15, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Atsushi Himeno, Haruyuki Sorada, Yukio Hayakawa, Takumi Mikawa
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Patent number: 9142775Abstract: A method of manufacturing a semiconductor device according to the present invention includes: forming a lower electrode above a substrate; forming, above the lower electrode, a first variable resistance layer comprising a first metal oxide; forming a step region in the first variable resistance layer by collision of ions excited by plasma; removing residue of the first variable resistance layer created in the forming of the step region; forming a second variable resistance layer which covers the step region of the first variable resistance layer, comprises a second metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide, and has a bend on a step formed along an edge of the step region; and forming an upper electrode above the second variable resistance layer.Type: GrantFiled: October 9, 2012Date of Patent: September 22, 2015Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yukio Hayakawa, Atsushi Himeno, Hideaki Murase, Yoshio Kawashima, Takumi Mikawa
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Patent number: 9130167Abstract: A method of manufacturing a nonvolatile memory device includes: forming a first electrode; forming, above the first electrode, a metal oxide material layer including a first metal oxide; forming a mask above part of the metal oxide material layer main surface; forming, in a region of the metal oxide material layer not covered by the mask, a high oxygen concentration region including a second metal oxide having a lower degree of oxygen deficiency than the first metal oxide; removing the mask; forming, above a first variable resistance layer including the high oxygen concentration region and a low oxygen concentration region that is a region of the metal oxide material layer other than the high oxygen concentration region, a second variable resistance layer including a third metal oxide having a lower degree of oxygen deficiency than the first metal oxide; and forming a second electrode above the second variable resistance layer.Type: GrantFiled: March 27, 2013Date of Patent: September 8, 2015Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hideaki Murase, Yoshio Kawashima, Atsushi Himeno, Takumi Mikawa
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Patent number: 9082967Abstract: A non-volatile memory device of the present invention comprises a first electrode; a variable resistance layer formed on and above the first electrode; a second electrode formed on and above the variable resistance layer; a side wall protective layer having an insulativity and covering a side wall of the first electrode, a side wall of the variable resistance layer and a side wall of the second electrode; and an electrically-conductive layer which is in contact with the second electrode; wherein the electrically-conductive layer covers an entire of the second electrode and at least a portion of the side wall protective layer located outward relative to the second electrode, when viewed from a thickness direction; and the side wall protective layer extends across the second electrode to a position above an upper end of the second electrode such that an upper end of the side wall protective layer is located above the upper end of the second electrode, when viewed from a side.Type: GrantFiled: September 26, 2013Date of Patent: July 14, 2015Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hideaki Murase, Yoshio Kawashima, Atsushi Himeno
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Publication number: 20150171142Abstract: A nonvolatile memory device includes an insulating layer, oxygen diffusion prevention layers disposed on the insulating layer, a plurality of contact plugs, each of the plurality of the contact plugs penetrating through each of the plurality of the oxygen diffusion prevention layers and at least a part of the insulating layer, and a plurality of resistance-variable elements, each of the plurality of the resistance-variable elements covering each of the plurality of the contact plugs exposed on surfaces of the oxygen diffusion prevention layers and being electrically connected to each of the plurality of the contact plugs Each of the oxygen diffusion prevention layers is provided only between the insulating layer and each of the plurality of the resistance-variable elements to correspond to each of the plurality of the contact plugs arranged for each of the plurality of the resistance-variable elements.Type: ApplicationFiled: December 3, 2014Publication date: June 18, 2015Inventors: YOSHIO KAWASHIMA, YUKIO HAYAKAWA, ATSUSHI HIMENO
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Publication number: 20150171324Abstract: A method of manufacturing a variable resistance nonvolatile memory device includes: forming, above a substrate, a metal-semiconductor-metal (MSM) diode element; forming a variable resistance element on the MSM diode element; forming a first oxygen barrier layer which covers a side wall of a semiconductor layer of the MSM diode element, and does not cover at least part of a side wall of a variable resistance layer of the variable resistance element; and oxidizing the side wall of the variable resistance layer which is exposed without being covered by the first oxygen barrier layer.Type: ApplicationFiled: January 10, 2013Publication date: June 18, 2015Applicant: Panasonic CorporationInventors: Takumi Mikawa, Atsushi Himeno, Hideaki Murase
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Patent number: 8952350Abstract: A non-volatile memory device of the present invention comprises a first electrode; a variable resistance layer formed on and above the first electrode; a second electrode formed on and above the variable resistance layer; a side wall protective layer having an insulativity and covering a side wall of the first electrode, a side wall of the variable resistance layer and a side wall of the second electrode; and an electrically-conductive layer connected to the second electrode; the non-volatile memory device including a connection layer which is provided between the second electrode and the electrically-conductive layer to connect the second electrode and the electrically-conductive layer to each other, and comprises an electrically-conductive material different from a material constituting the electrically-conductive layer; wherein the side wall protective layer extends across the second electrode to a position which is above an upper end of the second electrode and below an upper end of the connection layer sType: GrantFiled: September 26, 2013Date of Patent: February 10, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Hideaki Murase, Yoshio Kawashima, Atsushi Himeno
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Publication number: 20140197368Abstract: A nonvolatile memory element including: a first electrode; a second electrode; a variable resistance layer that is between the first electrode and the second electrode and includes, as stacked layers, a first variable resistance layer connected to the first electrode and a second variable resistance layer connected to the second electrode; and a side wall protecting layer that has oxygen barrier properties and covers a side surface of the variable resistance layer. The first variable resistance layer includes a first metal oxide and a third metal oxide formed around the first metal oxide and having an oxygen deficiency lower than that of the first metal oxide, and the second variable resistance layer includes a second metal oxide having an oxygen deficiency lower than that of the first metal oxide.Type: ApplicationFiled: September 10, 2012Publication date: July 17, 2014Applicant: Panasonic CorporationInventors: Shinichi Yoneda, Takumi Mikawa, Satoru Ito, Yukio Hayakawa, Atsushi Himeno
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Publication number: 20140145136Abstract: A non-volatile memory device of the present invention comprises a first electrode; a variable resistance layer formed on and above the first electrode; a second electrode formed on and above the variable resistance layer; a side wall protective layer having an insulativity and covering a side wall of the first electrode, a side wall of the variable resistance layer and a side wall of the second electrode; and an electrically-conductive layer which is in contact with the second electrode; wherein the electrically-conductive layer covers an entire of the second electrode and at least a portion of the side wall protective layer located outward relative to the second electrode, when viewed from a thickness direction; and the side wall protective layer extends across the second electrode to a position above an upper end of the second electrode such that an upper end of the side wall protective layer is located above the upper end of the second electrode, when viewed from a side.Type: ApplicationFiled: September 26, 2013Publication date: May 29, 2014Applicant: PANASONIC CORPORATIONInventors: Hideaki MURASE, Yoshio KAWASHIMA, Atsushi HIMENO
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Publication number: 20140113430Abstract: A method of manufacturing a semiconductor device according to the present invention includes: forming a lower electrode above a substrate; forming, above the lower electrode, a first variable resistance layer comprising a first metal oxide; forming a step region in the first variable resistance layer by collision of ions excited by plasma; removing residue of the first variable resistance layer created in the forming of the step region; forming a second variable resistance layer which covers the step region of the first variable resistance layer, comprises a second metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide, and has a bend on a step formed along an edge of the step region; and forming an upper electrode above the second variable resistance layer.Type: ApplicationFiled: October 9, 2012Publication date: April 24, 2014Applicant: PANASONIC CORPORATIONInventors: Yukio Hayakawa, Atsushi Himeno, Hideaki Murase, Yoshio Kawashima, Takumi Mikawa
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Publication number: 20140110659Abstract: A method of manufacturing a nonvolatile memory device includes: forming a first electrode; forming, above the first electrode, a metal oxide material layer including a first metal oxide; forming a mask above part of the metal oxide material layer main surface; forming, in a region of the metal oxide material layer not covered by the mask, a high oxygen concentration region including a second metal oxide having a lower degree of oxygen deficiency than the first metal oxide; removing the mask; forming, above a first variable resistance layer including the high oxygen concentration region and a low oxygen concentration region that is a region of the metal oxide material layer other than the high oxygen concentration region, a second variable resistance layer including a third metal oxide having a lower degree of oxygen deficiency than the first metal oxide; and forming a second electrode above the second variable resistance layer.Type: ApplicationFiled: March 27, 2013Publication date: April 24, 2014Applicant: Panasonic CorporationInventors: Hideaki Murase, Yoshio Kawashima, Atsushi Himeno, Takumi Mikawa
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Publication number: 20140097396Abstract: A non-volatile memory device of the present invention comprises a first electrode; a variable resistance layer formed on and above the first electrode; a second electrode formed on and above the variable resistance layer; a side wall protective layer having an insulativity and covering a side wall of the first electrode, a side wall of the variable resistance layer and a side wall of the second electrode; and an electrically-conductive layer connected to the second electrode; the non-volatile memory device including a connection layer which is provided between the second electrode and the electrically-conductive layer to connect the second electrode and the electrically-conductive layer to each other, and comprises an electrically-conductive material different from a material constituting the electrically-conductive layer; wherein the side wall protective layer extends across the second electrode to a position which is above an upper end of the second electrode and below an upper end of the connection layer sType: ApplicationFiled: September 26, 2013Publication date: April 10, 2014Applicant: PANASONIC CORPORATIONInventors: Hideaki MURASE, Yoshio KAWASHIMA, Atsushi HIMENO
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Patent number: 8581225Abstract: A manufacturing method includes forming, on a substrate, lower layer copper lines each being shaped into a strip, forming electrode seed layers each being shaped into a strip, on the respective lower layer copper lines using electroless plating, forming an interlayer insulating layer above the electrode seed layers, forming, in the interlayer insulating layer, memory cell holes, penetrating through the interlayer insulating layer and extending to the electrode seed layers, forming noble metal electrode layers on the electrode seed layers exposed in the respective memory cell holes using the electroless plating, forming, in the respective memory cell holes, variable resistance layers connected to the noble electrode layers, and forming, above the interlayer insulating layer and the variable resistance layers, upper layer copper lines each being shaped into a strip, connected to a corresponding one of the variable resistance layers, and crossing the lower layer copper lines.Type: GrantFiled: April 26, 2011Date of Patent: November 12, 2013Assignee: Panasonic CorporationInventors: Atsushi Himeno, Haruyuki Sorada, Takumi Mikawa
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Patent number: 8471235Abstract: A nonvolatile memory element includes a substrate; a lower electrode layer and a resistive layer sequentially formed on the substrate; a resistance variable layer formed on the resistive layer; a wire layer formed above the lower electrode layer; an interlayer insulating layer disposed between the substrate and the wire layer and covering at least the lower electrode layer and the resistive layer, the interlayer insulating layer being provided with a contact hole extending from the wire layer to the resistance variable layer; and an upper electrode layer formed inside the contact hole such that the upper electrode layer is connected to the resistance variable layer and to the wire layer; resistance values of the resistance variable layer changing reversibly in response to electric pulses applied between the lower electrode layer and the upper electrode layer.Type: GrantFiled: December 4, 2009Date of Patent: June 25, 2013Assignee: Panasonic CorporationInventors: Yoshio Kawashima, Takumi Mikawa, Zhiqiang Wei, Atsushi Himeno