Abstract: In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

Abstract: In a semiconductor apparatus having a PNP bipolar transistor and high voltage resistance, there is formed an oxide insulating layer in the surface region of a P-type semiconductor substrate. In the above semiconductor substrate is formed a P-type collector layer so that at least a part of the P-type collector layer is in contact with said oxide insulating layer. In the surface region of said P-type collector layer is formed a P-type collector contact layer. An N-type base layer is formed in that region on the surface side of said P-type collector layer in which said P-type collector contact layer does not exist. A P-type emitter layer is formed on the surface side of said N-type base layer.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment. P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: In a semiconductor apparatus having a PNP bipolar transistor and high voltage resistance, there is formed an oxide insulating layer in the surface region of a P-type semiconductor substrate. In the above semiconductor substrate is formed a P-type collector layer so that at least a part of the P-type collector layer is in contact with said oxide insulating layer. In the surface region of said P-type collector layer is formed a P-type collector contact layer. An N-type base layer is formed in that region on the surface side of said P-type collector layer in which said P-type collector contact layer does not exist. A P-type emitter layer is formed on the surface side of said N-type base layer.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment. P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: An unsymmetrical MOS device is disclosed which includes a semiconductor layer of a first conductive type having a surface having a first area and a second area which is offset from the first area; a gate insulator layer located on the first area of the surface of the semiconductor layer; a gate electrode located on the gate insulator layer; and a source region of a second conductive type and a drain region of the second conductive type each located in the semiconductor layer below the second area of the surface. The electric resistance of an area between the first area of the surface and the surface of the source region is smaller than the electric resistance of an area between the first area of the surface and the surface of the drain region.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: A semiconductor device includes an input/output terminal, an internal circuit connected to the input/output terminal, a first terminal for providing a first electrical potential, and a second terminal for providing a second electrical potential which is lower than the first electrical potential, the device further including: a first n-channel MOS transistor having a drain connected to the input/output terminal, a source connected to the second terminal, and a gate to be electrically connected to the first terminal; and a first switching element for switching between an electrically conductive state and a non-conductive state between the drain and the gate of the first n-channel MOS transistor, the switching element forming the electrically conductive state between the drain and the gate of the first n-channel MOS transistor when 1) a surge voltage lower than the first electrical potential is applied to the input/output terminal, and 2) an electrical potential difference between the drain and the gate of the f

Abstract: A MOS transistor for protection against electrostatic discharge includes a semiconductor substrate; an island including a source region and a drain region provided in the semiconductor substrate; an isolation region provided in the semiconductor substrate so as to surround the island; a gate insulating layer provided on the semiconductor substrate; a gate electrode provided on the gate insulating layer; and a distributing device for distributing an electric current generated by an electrostatic voltage applied to the drain region into the drain region.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: Insulating films formed on side walls of a gate electrode are removed for a self-alignment to selectively implant impurities only into end portions of a source region and a drain region. Therefore, p.sup.+ -type semiconductor regions are selectively formed only on sides near a channel region of the source and the drain regions. A punch through of the source or drain region is prevented by the p.sup.+ -type semiconductor regions controlling an inversion threshold voltage. Therefore, the impurity concentration of the p-type substrate can be settled low, and the semiconductor transistor device can be miniaturized without increasing a parasitic junction capacitance. Moreover, since the impurity concentration in the channel region is ununiform, a drivability of the transistor can be increased. As a result, a semiconductor transistor device with a high withstand voltage and a high drivability in which the inversion threshold voltage can be easily controlled, and a method for producing the same are provided.

Abstract: A fabrication method for semiconductor devices connecting a multi-crystal semiconductor thin film and a semiconductor region including a high density of an impurity formed in a single crystal semiconductor substrate. After forming a N-type semiconductor region as the emitter by ion implanting, for instance, as into a P-type semiconductor region as the base, a polysilicon thin film 114 is deposited so as to be implanted with As ions and then heat treated. In this case, an amorphous portion of the N-type semiconductor region and an amorphous silicon thin film in contact therewith are transformed by solid phase epitaxial growth so as to form a single crystal semiconductor region, a single-crystalline silicon thin film, and a polysilicon thin film, thus forming a bipolar element having an emitter.

Abstract: There is disclosed a method for manufacturing a bipolar semiconductor device in which emitter region and active base region are formed by implanting impurities of first and second conduction types in a first semiconductor region of the first conduction type to be a collector through a non-single crystalline semiconductor thin film, a second semiconductor thin film is formed on the first semiconductor thin film, and an impurity of the first conduction type is introduced in the second semiconductor thin film after patterning the first and second semiconductor thin film so as to form an emitter electrode.

Abstract: A method of fabricating a semiconductor device having gate-drain overlap MOSFETs in which side surfaces of upper portions of gate lines are anisotropically etched using a buffer film as an etch stop is disclosed. An insulating film as a gate insulator is formed on a semiconductor layer of a first conductivity type. A first conductive film is formed on the gate insulator. A buffer film having openings in gate line regions is formed on the first conductive film. A second conductive film is formed on the buffer film. The second conductive film is patterned into wiring shape to form upper portions of gate lines covering the openings of the buffer film. Ions of a second conductivity type are implanted into the semiconductor layer using the upper portions of the gate lines as an implant mask to form sources and drains in the semiconductor layer. Sidewall spacers are formed on the sides of the upper portions of the gate lines.

Abstract: A method for producing field-effect type semiconductor devices is disclosed which includes the steps of: forming a gate insulator film on a semiconductor substrate; forming a conductor film on the gate insulator film; and implanting impurity ions in the semiconductor substrate through the gate insulator film and the conductor film for the purpose of controlling a threshold voltage of the device, wherein the conductor film is employed as a gate electrode of the device. The method of this invention has the excellent advantages of readily controlling a threshold voltage of field-effect type semiconductor devices and of preventing the scatter of the threshold voltage values. An alternative embodiment employs formation of a second conductor film and implantation from an inclined direction.

Abstract: An operating switch has a push button provided in a housing of a switch body for operation when depressed by an operating lever pivoted on the housing. The operation of the push button causes a switch arrangement to be turned by a turning arrangement so that a movable contact is engaged with or disengaged from a stationary contact. The turning arrangement includes a sliding cam disposed along the interior face of the push button and having cam parts engageable with engaging projections of a pivotable actuator coupled resiliently to the switching arrangement upon performing a sliding movement in a direction perpendicular to the direction of movement of the push button.

Abstract: In a semiconductor integrated circuit device using a field effect transistor, such as MOS, having the end part of the drain overlapped with the gate electrode, a novel gate-drain overlap structure of excellent performance and reliability is presented. A manufacturing method for this device is also presented.