Abstract: The invention provides a high frequency amplifier in which a variable attenuator consisting of a bypass FET, which has a drain connected to a first-stage amplifying FET via a resistor, and a source grounded via a capacitor, is located on a main signal line leading to the gate of the amplifying FET, in order to control the gate potential of a bypass FET using a gain control voltage source, thereby varying the gain of the amplifier.

Abstract: A switching circuit is made by serially connecting two field effect transistors in series in a small-signal transmission path, each of the transistors being applied with a substantially equal voltage, so as to lower a voltage applied to each of the FETs in the OFF state by voltage division, with the result that a high withstand voltage of the transmission path can be attained and a linear output can be obtained even when a large electric power is transmitted.

Abstract: A semiconductor integrated circuit according to this invention is characterized by comprising a flip-flop having input terminal means and output terminal means, at least one input gate means having output terminal means connected to the input terminal means, which supplies data to this input terminal means under the control of clock, and at least one output buffer means having input terminal means connected to the output terminal means, to which the output signal of the flip-flop is supplied and which is connected to the output terminal means of the input gate means to receive the data from this input gate means to provide an advance read function.

Abstract: A standard cell type gallium arsenide logic integrated circuit device includes arrays of standard cells connected to each other on a chip substrate. Each of the standard cells includes a plurality of gallium arsenide logic gates of previously selected type such as NOR gates and an inverter. The logic gate has a direct-coupled type FET logic circuit structure. In each of the standard cells, level-shift circuits are provided only for inputs of those logic gates which are directly connected to connection terminals directly associated with the other standard cell. The level-shift circuits enhance the swing width of a logic signal transmitted between the standard cells which are associated with one another, thereby increasing the operation margin. Such a level-shift circuit is not provided for internal interconnection wirings between the logic gates inside the standard cell.

Abstract: A differential amplifier includes first and second normally off type MESFETs, which constitute a differential switching stage, sources of which are commonly connected to a current source, and gates of which are supplied with a signal input potential and a reference potential, respectively, third and fourth normally on type MESFETs connected at loads between the first MESFET and a voltage source and between the second MESFET and the voltage source, fifth and sixth normally off type MESFETs gates of which are connected to the drains of the first and second MESFETs, respectively, and drains of which are connected to the voltage source, and seventh and eighth MESFETs drains of which are connected to sources of the fifth and sixth MESFETs and output first and second output potentials and gates of which are applied with potentials having levels corresponding to the second and first output potentials, respectively.