Patents by Inventor Atsushi Kanda
Atsushi Kanda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170057080Abstract: A robot system for carrying out a plurality of operations during assembly or maintenance of an aircraft or spacecraft includes a first robot having a base portion, a movable robot arm having a first coupling portion, and a first control means for controlling the robot arm, a plurality of second robots having movement means, a drive portion operable to drive the movement means, a tool portion having a tool for carrying out a specific one of the operations, a second coupling portion adapted to be selectively and releasably coupled with the first coupling portion in a predetermined positional relationship, and a second control means for controlling the respective second robot. The first and second control means are adapted to control the drive portion of one of the second robots and the robot arm to couple the first coupling portion and the respective second coupling portion in the predetermined positional relationship.Type: ApplicationFiled: August 24, 2016Publication date: March 2, 2017Applicant: Airbus Operations GmbHInventors: Ingo Krohne, Robert Alexander Goehlich, Yoshiyasu Hirano, Yuichiro Aoki, Yutaka Iwahori, Atsushi Kanda
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Publication number: 20140253308Abstract: A vehicular emergency report apparatus includes a collision detection section, an emergency report section, and a counting section. The collision detection section detects an occurrence of a vehicle-pedestrian collision in which a vehicle collides with one or more pedestrians. The emergency report section reports the vehicle-pedestrian collision to an emergency center when the collision detection section detects the occurrence of the vehicle-pedestrian collision. The counting section counts the number of the one or more pedestrians in collision with the vehicle. The emergency report section transmits the number of the one or more pedestrians in collision with the vehicle to the emergency center when reporting the vehicle-pedestrian collision to the emergency center.Type: ApplicationFiled: March 3, 2014Publication date: September 11, 2014Applicant: DENSO CORPORATIONInventor: Atsushi Kanda
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Patent number: 8714707Abstract: A method of making a hole in a substrate having a first surface and a second surface opposing the first surface and on which the hole is formed, includes forming a first depression in which the first depression is formed at the first surface of the substrate; forming a film in which the film is formed at the first depression; forming a second depression in which the second depression is formed at a location opposing the first depression of the second surface; and forming a hole in which the film is removed, the first depression and the second depression communicate with each other and thereby the hole is formed, wherein the second depression includes a plurality of straight lines and arcs in a plan view.Type: GrantFiled: June 12, 2012Date of Patent: May 6, 2014Assignee: Seiko Epson CorporationInventors: Atsushi Kanda, Junichi Takeuchi
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Publication number: 20120327161Abstract: A method of making a hole in a substrate having a first surface and a second surface opposing the first surface and on which the hole is formed, includes forming a first depression in which the first depression is formed at the first surface of the substrate; forming a film in which the film is formed at the first depression; forming a second depression in which the second depression is formed at a location opposing the first depression of the second surface; and forming a hole in which the film is removed, the first depression and the second depression communicate with each other and thereby the hole is formed, wherein the second depression includes a plurality of straight lines and arcs in a plan view.Type: ApplicationFiled: June 12, 2012Publication date: December 27, 2012Applicant: SEIKO EPSON CORPORATIONInventors: Atsushi KANDA, Junichi TAKEUCHI
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Patent number: 8174838Abstract: A display device includes a circuit board having a plurality of pixels arranged thereon, each pixel having a plurality of light emitting elements, a driving circuit driving the light emitting elements, a case housing the above, a frame having flanges at a circuit board side of the case to block external light toward the light emitting elements, and a shield disposed between the frame and the case to block electromagnetic noise. A screw is inserted into a through hole and placed into a screw receiving portion to fix the frame and the case. The screw receiving portion has a cylindrical metal portion housing the screw and electrically connecting the screw and the shield, and a resin portion interposed between the placed screw and the inner wall surface of the cylindrical metal portion.Type: GrantFiled: April 24, 2009Date of Patent: May 8, 2012Assignee: Nichia CorporationInventors: Atsushi Kanda, Tsuzuki Takahashi
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Publication number: 20120079793Abstract: An objective of the present invention is to provide a bag sealing tape which can be repeatedly used without damaging a banded object such as a bag or the like when the object is opened, and which does not have to be separated for disposal; and a banding device and a banding method using the bag sealing tape. The bag sealing tape of the present invention includes adhesion zones and non-adhesion zones, and the adhesion zones are disposed on the surface of a base film in a stepping stone manner in a length direction of the base film.Type: ApplicationFiled: October 4, 2011Publication date: April 5, 2012Applicant: KYOWA LIMITEDInventors: Hidekazu Oue, Yusuke Akiba, Tatsuya Sugiyama, Atsushi Kanda, Takaaki Tamada, Tadashi Matsumoto, Masaharu Taniguchi, Takeshi Fujii
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Publication number: 20090268416Abstract: A display device includes a circuit board having a plurality of pixels arranged thereon, each pixel having a plurality of light emitting elements, a driving circuit driving the light emitting elements, a case housing the above, a frame having flanges at a circuit board side of the case to block external light toward the light emitting elements, and a shield disposed between the frame and the case to block electromagnetic noise. A screw is inserted into a through hole and placed into a screw receiving portion to fix the frame and the case. The screw receiving portion has a cylindrical metal portion housing the screw and electrically connecting the screw and the shield, and a resin portion interposed between the placed screw and the inner wall surface of the cylindrical metal portion.Type: ApplicationFiled: April 24, 2009Publication date: October 29, 2009Inventors: Atsushi KANDA, Tsuzuki Takahashi
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Patent number: 7511539Abstract: A driver circuit includes first and second three-terminal active elements, and first and second delay units. The first and second three-terminal active elements are series-connected. Each of the first and second three-terminal active elements has an amplification function and first, second, and third electrodes. The second and third electrodes of each three-terminal active element are series-connected between the first and second potentials. The first and second delay units receive the same input signal. The outputs of the first and second delay units are respectively connected to the first electrodes of the first and second three-terminal active elements. The delay amount of the second delay unit is larger than that of the first delay unit. The delay amount of the first delay unit is a finite value including zero.Type: GrantFiled: January 23, 2007Date of Patent: March 31, 2009Assignee: Nippon Telegraph and Telephone CorporationInventors: Yohtaro Umeda, Atsushi Kanda
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Publication number: 20080258298Abstract: Embodiments include a semiconductor device comprising: a pad formed on an insulating layer and having an electric connection region with external components; and a protective insulating layer which has an aperture for exposing the electric connection region. The protective insulating layer may include a first insulating layer and a second insulating layer, and side surfaces of these insulating layers are exposed to the aperture. At least part of the side surfaces surrounding the electric connection region have a tapered configuration at an acute angle to a top surface of the pad. This semiconductor device not only enables reduction of the fabrication steps, but also provides a reliable passivation structure for a pad with sufficient thickness and stress relaxation characteristics.Type: ApplicationFiled: September 19, 2007Publication date: October 23, 2008Inventor: Atsushi Kanda
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Publication number: 20080061380Abstract: The present invention provides a technique for efficiently forming a high-breakdown voltage transistor and a low-breakdown voltage transistor on the same substrate while reducing the deterioration of each transistors' characteristics. At first, an insulating film is formed. The insulating film portions above the drain and source formation regions for the high-breakdown voltage transistor are thicker than those for the low-breakdown voltage transistor. Next, gates are formed on the insulating film. Then sidewalls are formed on the sides of the low-breakdown voltage transistor gate, and apertures are made in the insulating film portions above the drain and source formation regions for each transistor. When apertures are made in the relatively thick insulating film portions above the drain and source formation regions for the high-breakdown voltage transistor, etching is performed not to narrow widths of the sidewalls formed on the sides of the gate for the low-breakdown voltage transistor.Type: ApplicationFiled: October 31, 2007Publication date: March 13, 2008Applicant: Seiko Epson CorporationInventors: Atsushi Kanda, Yasushi Haga
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Publication number: 20080064169Abstract: The present invention provides a technique for efficiently forming a high-breakdown voltage transistor and a low-breakdown voltage transistor on the same substrate while reducing the deterioration of each transistors' characteristics. At first, an insulating film is formed. The insulating film portions above the drain and source formation regions for the high-breakdown voltage transistor are thicker than those for the low-breakdown voltage transistor. Next, gates are formed on the insulating film. Then sidewalls are formed on the sides of the low-breakdown voltage transistor gate, and apertures are made in the insulating film portions above the drain and source formation regions for each transistor. When apertures are made in the relatively thick insulating film portions above the drain and source formation regions for the high-breakdown voltage transistor, etching is performed not to narrow widths of the sidewalls formed on the sides of the gate for the low-breakdown voltage transistor.Type: ApplicationFiled: October 31, 2007Publication date: March 13, 2008Applicant: Seiko Epson CorporationInventors: Atsushi Kanda, Yasushi Haga
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Publication number: 20080048334Abstract: Embodiments include a semiconductor device comprising: a pad formed on an insulating layer and having an electric connection region with external components; and a protective insulating layer which has an aperture for exposing the electric connection region. The protective insulating layer may include a first insulating layer and a second insulating layer, and side surfaces of these insulating layers are exposed to the aperture. At least part of the side surfaces surrounding the electric connection region have a tapered configuration at an acute angle to a top surface of the pad. This semiconductor device not only enables reduction of the fabrication steps, but also provides a reliable passivation structure for a pad with sufficient thickness and stress relaxation characteristics.Type: ApplicationFiled: October 22, 2007Publication date: February 28, 2008Inventor: Atsushi Kanda
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Publication number: 20080042298Abstract: Embodiments include a semiconductor device comprising: a pad formed on an insulating layer and having an electric connection region with external components; and a protective insulating layer which has an aperture for exposing the electric connection region. The protective insulating layer may include a first insulating layer and a second insulating layer, and side surfaces of these insulating layers are exposed to the aperture. At least part of the side surfaces surrounding the electric connection region have a tapered configuration at an acute angle to a top surface of the pad. This semiconductor device not only enables reduction of the fabrication steps, but also provides a reliable passivation structure for a pad with sufficient thickness and stress relaxation characteristics.Type: ApplicationFiled: October 22, 2007Publication date: February 21, 2008Inventor: Atsushi KANDA
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Patent number: 7285863Abstract: Embodiments include a semiconductor device comprising: a pad formed on an insulating layer and having an electric connection region with external components; and a protective insulating layer which has an aperture for exposing the electric connection region. The protective insulating layer may include a first insulating layer and a second insulating layer, and side surfaces of these insulating layers are exposed to the aperture. At least part of the side surfaces surrounding the electric connection region have a tapered configuration at an acute angle to a top surface of the pad. This semiconductor device not only enables reduction of the fabrication steps, but also provides a reliable passivation structure for a pad with sufficient thickness and stress relaxation characteristics.Type: GrantFiled: October 12, 2004Date of Patent: October 23, 2007Assignee: Seiko Epson CorporationInventor: Atsushi Kanda
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Publication number: 20070120589Abstract: A driver circuit includes first and second three-terminal active elements, and first and second delay units. The first and second three-terminal active elements are series-connected. Each of the first and second three-terminal active elements has an amplification function and first, second, and third electrodes. The second and third electrodes of each three-terminal active element are series-connected between the first and second potentials. The first and second delay units receive the same input signal. The outputs of the first and second delay units are respectively connected to the first electrodes of the first and second three-terminal active elements. The delay amount of the second delay unit is larger than that of the first delay unit. The delay amount of the first delay unit is a finite value including zero.Type: ApplicationFiled: January 23, 2007Publication date: May 31, 2007Inventors: Yohtaro Umeda, Atsushi Kanda
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Patent number: 7187227Abstract: A driver circuit includes first and second three-terminal active elements, and first and second delay units. The first and second three-terminal active elements are series-connected. Each of the first and second three-terminal active elements has an amplification function and first, second, and third electrodes. The second and third electrodes of each three-terminal active element are series-connected between the first and second potentials. The first and second delay units receive the same input signal. The outputs of the first and second delay units are respectively connected to the first electrodes of the first and second three-terminal active elements. The delay amount of the second delay unit is larger than that of the first delay unit. The delay amount of the first delay unit is a finite value including zero.Type: GrantFiled: August 6, 2003Date of Patent: March 6, 2007Assignee: Nippon Telegraph and Telephone CorporationInventors: Yohtaro Umeda, Atsushi Kanda
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Patent number: 6916714Abstract: A procedure of manufacturing a semiconductor device according to the present invention first creates a gate electrode on a center portion of a gate oxide film formed on a substrate, forms a silicon oxide film over the whole surface of the substrate including the gate electrode, and etches the whole face of the silicon oxide film, so as to form a side wall of the silicon oxide film on a side face of the gate electrode. The procedure then implants an impurity ion according to a channel of a target MOS transistor, so as to specify a drain area and a source area. In the process of specifying the drain area and the source area, a resist is formed in advance on at least a peripheral portion of the gate oxide film in a high-breakdown-voltage MOS transistor, so as to prevent implantation of the impurity ion in an under-layer region below the peripheral portion of the gate oxide film.Type: GrantFiled: August 2, 2002Date of Patent: July 12, 2005Assignee: Seiko Epson CorporationInventors: Atsushi Kanda, Yasushi Haga
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Patent number: 6884868Abstract: This invention relates to new polypeptide compound represented by general formula (I), wherein R1, R2, R3, R4, R5 and R6 are as defined in the description or a salt thereof which has antimicrobial activities (especially, antifungal activities), inhibitory activity on ?-1,3-glucan synthase, to process for preparation thereof, to a pharmaceutical composition comprising the same, and to a method for prophylactic and/or therapeutic treatment of infectious diseases including Pneumocystis carinii infection (e.g. Pneumocystis carinii pneumonia) in a human being or an animal.Type: GrantFiled: April 25, 2000Date of Patent: April 26, 2005Assignee: Fujisawa Pharmaceutical Co., Ltd.Inventors: Takashi Tojo, Hidenori Ohki, Nobuyuki Shiraishi, Takahiro Matsuya, Hiroshi Matsuda, Kenji Murano, David Barrett, Takashi Ogino, Keiji Matsuda, Masaharu Ichihara, Norio Hashimoto, Atsushi Kanda, Atsushi Ohigashi
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Publication number: 20050046025Abstract: Embodiments include a semiconductor device comprising: a pad formed on an insulating layer and having an electric connection region with external components; and a protective insulating layer which has an aperture for exposing the electric connection region. The protective insulating layer may include a first insulating layer and a second insulating layer, and side surfaces of these insulating layers are exposed to the aperture. At least part of the side surfaces surrounding the electric connection region have a tapered configuration at an acute angle to a top surface of the pad. This semiconductor device not only enables reduction of the fabrication steps, but also provides a reliable passivation structure for a pad with sufficient thickness and stress relaxation characteristics.Type: ApplicationFiled: October 12, 2004Publication date: March 3, 2005Inventor: Atsushi Kanda
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Patent number: D622676Type: GrantFiled: September 19, 2007Date of Patent: August 31, 2010Assignee: Nichia CorporationInventors: Tsuyoshi Yasuoka, Atsushi Kanda