Abstract: The present invention provides a technique for efficiently forming a high-breakdown voltage transistor and a low-breakdown voltage transistor on the same substrate while reducing the deterioration of each transistors' characteristics. At first, an insulating film is formed. The insulating film protions above the drain and source formation regions fo rhte high-breakdown voltage transistor are thicker than those for the low-breakdown voltage transistor. Next, gates are formed on the insulating film. Then sidewalls are formed on the sides of the low-breakdown voltage transistor gate, and apertures are made in the insulating film portions above the drain and source formation regions for each transistor. When apertures are made in the relatively thick insulating film portions above the drain and source formation regions for the high-breakdown voltage transistor, etching is performed not to narrow widths of the sidewalls formed on the sides of the gate for the low-breakdown voltage transistor.

Abstract: Embodiments include a semiconductor device comprising: a pad formed on an insulating layer and having an electric connection region with external components; and a protective insulating layer which has an aperture for exposing the electric connection region. The protective insulating layer may include a first insulating layer and a second insulating layer, and side surfaces of these insulating layers are exposed to the aperture. At least part of the side surfaces surrounding the electric connection region have a tapered configuration at an acute angle to a top surface of the pad. This semiconductor device not only enables reduction of the fabrication steps, but also provides a reliable passivation structure for a pad with sufficient thickness and stress relaxation characteristics.

Abstract: The present invention provides a technique for efficiently forming a high-breakdown voltage transistor and a low-breakdown voltage transistor on the same substrate while reducing the deterioration of each transistor's characteristics. At first, an insulating film is formed. The insulating film portions above the drain and source formation regions for the high-breakdown voltage transistor are thicker than those for the low-breakdown voltage transistor. Next, gates are formed on the insulating film. Then sidewalls are formed on the sides of the low-breakdown voltage transistor gate, and apertures are made in the insulating film portions above the drain and source formation regions for each transistor. When apertures are made in the relatively thick insulating film portions above the drain and source formation regions for the high-breakdown voltage transistor, etching is performed not to narrow widths of the sidewalls formed on the sides of the gate for the low-breakdown voltage transistor.

Abstract: A driver circuit includes first and second three-terminal active elements, and first and second delay units. The first and second three-terminal active elements are series-connected. Each of the first and second three-terminal active elements has an amplification function and first, second, and third electrodes. The second and third electrodes of each three-terminal active element are series-connected between the first and second potentials. The first and second delay units receive the same input signal. The outputs of the first and second delay units are respectively connected to the first electrodes of the first and second three-terminal active elements. The delay amount of the second delay unit is larger than that of the first delay unit. The delay amount of the first delay unit is a finite value including zero.

Abstract: Among first and second oxide films 110 and 112 formed on a substrate 100, the oxide film in a low-breakdown-voltage transistor area LV is all etched off, while the whole surface of the oxide film in a high-breakdown-voltage transistor area HV is left intact. A sixth oxide film 119 for defining side walls is subsequently formed on the whole surface of the substrate 100 in a greater thickness of approximately 2000 angstrom than a standard thickness. Over-etching of the sixth oxide film 119 defines side walls 119SW. Non-required portions of the oxide film 112 are then etched off with a resist R15A. This causes a drain-source forming region, which is expected to form a drain area and a source area, to be open in an element forming region in a high-breakdown-voltage nMOS area HVn. The resist R15A is not removed but is used continuously, and an n-type impurity ion is implanted into the open drain-source forming region.

Abstract: Among first and second oxide films 110 and 112 formed on a substrate 100, the oxide film in a low-breakdown-voltage transistor area LV is all etched off, while the whole surface of the oxide film in a high-breakdown-voltage transistor area HV is left intact. A sixth oxide film 119 to define a side wall is subsequently formed on the whole surface of the substrate 100, and a resist R17 is formed over the whole high-breakdown-voltage transistor area HV. Over-etching of the low-breakdown-voltage transistor area LV is carried out to make the surface of the substrate 100 exposed and to define the side wall only in the low-breakdown-voltage transistor area LV. The oxide film 119 is made to remain in the high-breakdown-voltage transistor area HV. Non-required portions of the oxide films 119 and 112 are then etched off with a resist R15B.

Abstract: The present invention provides a technique for efficiently forming a high-breakdown voltage transistor and a low-breakdown voltage transistor on the same substrate while reducing the deterioration of each transistor's characteristics. At first, an insulating film is formed. The insulating film portions above the drain and source formation regions for the high-breakdown voltage transistor are thicker than those for the low-breakdown voltage transistor. Next, gates are formed on the insulating film. Then sidewalls are formed on the sides of the low-breakdown voltage transistor gate, and apertures are made in the insulating film portions above the drain and source formation regions for each transistor. When apertures are made in the relatively thick insulating film portions above the drain and source formation regions for the high-breakdown voltage transistor, etching is performed not to narrow widths of the sidewalls formed on the sides of the gate for the low-breakdown voltage transistor.

Abstract: Among first and second oxide films 110 and 112 formed on a substrate 100, the oxide film in a low-breakdown-voltage transistor area LV is all etched off, while the whole surface of the oxide film in a high-breakdown-voltage transistor area HV is left intact. A sixth oxide film 119 for defining side walls is subsequently formed on the whole surface of the substrate 100 in a greater thickness of approximately 2000 angstrom than a standard thickness. Over-etching of the sixth oxide film 119 defines side walls 119SW. Non-required portions of the oxide film 112 are then etched off with a resist R15A. This causes a drain-source forming region, which is expected to form a drain area and a source area, to be open in an element forming region in a high-breakdown-voltage nMOS area HVn. The resist R15A is not removed but is used continuously, and an n-type impurity ion is implanted into the open drain-source forming region.

Abstract: Among first and second oxide films 110 and 112 formed on a substrate 100, the oxide film in a low-breakdown-voltage transistor area LV is all etched off, while the whole surface of the oxide film in a high-breakdown-voltage transistor area HV is left intact. A sixth oxide film 119 to define a side wall is subsequently formed on the whole surface of the substrate 100, and a resist R17 is formed over the whole high-breakdown-voltage transistor area HV. Over-etching of the low-breakdown-voltage transistor area LV is carried out to make the surface of the substrate 100 exposed and to define the side wall only in the low-breakdown-voltage transistor area LV. The oxide film 119 is made to remain in the high-breakdown-voltage transistor area HV. Non-required portions of the oxide films 119 and 112 are then etched off with a resist R15B.

Abstract: A procedure of manufacturing a semiconductor device according to the present invention first creates a gate electrode on a center portion of a gate oxide film formed on a substrate, forms a silicon oxide film over the whole surface of the substrate including the gate electrode, and etches the whole face of the silicon oxide film, so as to form a side wall of the silicon oxide film on a side face of the gate electrode. The procedure then implants an impurity ion according to a channel of a target MOS transistor, so as to specify a drain area and a source area. In the process of specifying the drain area and the source area, a resist is formed in advance on at least a peripheral portion of the gate oxide film in a high-breakdown-voltage MOS transistor, so as to prevent implantation of the impurity ion in an under-layer region below the peripheral portion of the gate oxide film.

Abstract: A compound of the following formula (II) and a process for preparing of the compound of the following formula (I) its preparation wherein R1 is carboxy or protected carboxy; R2 is lower alkoxy or higher alkoxy; A1 is a divalent aromatic ring, a divalent heterocyclic group or a divalent cyclo(lower)alkane; and A2 is a divalent aromatic ring, a divalent heterocyclic group or a divalent cyclo(lower)alkane, or a salt thereof. The process comprises, reacting a compound of the formula (III): wherein R1, R2, A1 and A2 are each as defined above or a salt thereof, with an acid ammonium salt to give a compound of the formula (II).

Abstract: A new industrial process excellent in yield and purity for preparing a compound of the formula: or a salt thereof in a less number of steps with a synthetic pathway without proceeding via nitroso compounds, wherein R1 is lower aryl, ar(lower)alkoxy or heterocyclic group, each of which may be substituted with halogen, and R2 is cyclo(lower)alkyl, aryl or ar(lower)alkyl, each of which may be substituted with halogen.

Abstract: A compound of formula (1) or a salt thereof: wherein R1 is a carboxy or a protected carboxy; R2 is a lower alkoxy or a higher alkoxy; A1 is a divalent aromatic ring, a divalent heterocyclic group or a divalent cyclo(lower)alkane; and A2 a divalent aromatic ring, a divalent heterocyclic group or a divalent cyclo(lower)alkane; is prepared by reacting a compound of formula (III) or a salt thereof with acid ammonium salt: wherein R1, R2, A1 and A2 are each as defined above; to give a compound of formula (II) or a salt thereof which is further reacted with a salt of hydroxylamine: wherein R1, R2, A1 and A2 are each as defined above.

Abstract: The present invention relates to a novel process for preparing of the compound of the following formula (I)

Abstract: An aluminum nitride multilayered wiring substrate and a method of manufacturing the wiring substrate are provided. The wiring substrate is provided with the high dielectric layer. Although the wiring substrate has no excessively multilayered structure, high capacitance can be easily obtained. The multilayered wiring substrate is a laminated body of an upper substrate layer, a capacitor layer and a lower substrate layer. Three aluminum nitride layers composing the upper substrate layer have interior peripheries arranged in a step fashion stepping down toward the center of the multilayered wiring substrate. The central part of the upper substrate layer is thinner than the periphery. The surfaces and inside of the upper substrate layer are provided with conductive layers. The capacitor layer is a laminated body of two high dielectric layers formed of aluminum nitride with titanium nitride added thereto for raising the specific dielectric constant.

Abstract: An aluminum nitride multilayered wiring substrate and a method of manufacturing the wiring substrate are provided. The wiring substrate is provided with the high dielectric layer. Although the wiring substrate has no excessively multilayered structure, high capacitance can be easily obtained. The multilayered wiring substrate is a laminated body of an upper substrate layer, a capacitor layer and a lower substrate layer. Three aluminum nitride Layers composing the upper substrate layer have interior peripheries arranged in a step fashion stepping down toward the center of the multilayered wiring substrate. The central part of the upper substrate layer is thinner than the periphery. The surfaces and inside of the upper substrate layer are provided with conductive layers. The capacitor layer is a laminated body of two high dielectric layers formed of aluminum nitride with titanium nitride added thereto for raising the specific dielectric constant.

Abstract: An aluminum nitride sintered body comprising aluminum nitride as a main component, a titanium compound, and an yttrium compound, wherein when the content of titanium and the content of yttrium both in terms of percentage by weight based on the aluminum nitride sintered body are plotted on an x-y coordinate system, with the titanium content as the x axis and the yttrium content as the y axis, the titanium content and the yttrium content each is within a region surrounded by the lines connecting points A and B, B and C, C and D, D and E, and E and A, inclusive of the lines the points A, B, C, D and E being:A (0.2, 2.0)B (0.2, 6.5)C (1.0, 10.25)D (2.2, 10.25)E (2.2, 5.0).

Abstract: A joint for joining a ceramic shaft to a metal sleeve includes a gap separating the outer surface of the ceramic shaft from the inner surface of an overlapping portion of a metal sleeve. A brazing filler material is provided in only the portion of the gap proximate the end of the ceramic shaft to accommodate stresses caused by the different thermal characteristics of the metal sleeve and the ceramic shaft.

Abstract: A boiling refrigerant-type cooling system for cooling an electric apparatus includes a refrigerant containing chamber in which the electric apparatus is disposed, a condensing chamber, and a vapor reservoir all in flow communication with each other. A cooling chamber open to the atmosphere adjoins the condensing chamber. A laminated partition separates the cooling chamber from the condensing chamber. The electric apparatus is electrically connected through a sealed opening in the refrigerant containing chamber.

Abstract: The bond strength between a silicon carbide substrate and a metal layer comprised of a series of metal films is improved without detrimentally affecting other properties of such a device by interposing a layer of silicon, Si.sub.2 Mo or mixtures thereof between the substrate and the first metal film in the layer which is preferably Ti, Zr or Hf.