Patents by Inventor Atsushi Kasuya

Atsushi Kasuya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200396836
    Abstract: A resin multilayer board includes a substrate including a stack of resin layers, and a first metal pin including a first end portion exposed at a first main surface of the substrate and penetrating through at least one of the resin layers in a thickness direction, wherein a gap is provided at a portion of an interface between a lateral side of the first metal pin and the resin layer.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 17, 2020
    Inventors: Atsushi KASUYA, Yusuke KAMITSUBO
  • Patent number: 10813218
    Abstract: A resin multilayer board includes a substrate including a stack of resin layers, and a first metal pin including a first end portion exposed at a first main surface of the substrate and penetrating through at least one of the resin layers in a thickness direction, wherein a gap is provided at a portion of an interface between a lateral side of the first metal pin and the resin layer.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: October 20, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Atsushi Kasuya, Yusuke Kamitsubo
  • Publication number: 20200245460
    Abstract: A multilayer substrate includes a base body including a first main surface, a first external electrode provided on the first main surface and made of metal foil, a first interlayer connection conductor, and a second interlayer connection conductor having higher conductivity than the first interlayer connection conductor. The base body includes insulating base material layers that are stacked on one another. The first interlayer connection conductor is provided at least in an insulating base material layer on which the first external electrode is provided, and is connected to the first external electrode. The second interlayer connection conductor is disposed inside the base body, and is connected to the first external electrode through the first interlayer connection conductor.
    Type: Application
    Filed: April 16, 2020
    Publication date: July 30, 2020
    Inventors: Hiromasa KOYAMA, Ryosuke TAKADA, Atsushi KASUYA
  • Publication number: 20200178391
    Abstract: A resin multilayer board includes a substrate including a stack of resin layers, and a first metal pin including a first end portion exposed at a first main surface of the substrate and penetrating through at least one of the resin layers in a thickness direction, wherein a gap is provided at a portion of an interface between a lateral side of the first metal pin and the resin layer.
    Type: Application
    Filed: February 12, 2020
    Publication date: June 4, 2020
    Inventors: Atsushi KASUYA, Yusuke KAMITSUBO
  • Patent number: 10593989
    Abstract: An object of the present invention is to provide a method for manufacturing an aluminum plate which is simple, is high in productiveness, allows the use of arbitrary aluminum materials, and can be suitably used for collectors having excellent adhesiveness to active material layers, a collector for a storage device, and a storage device. The method for manufacturing an aluminum plate of the present invention is a method for manufacturing an aluminum plate having an aluminum substrate having a plurality of through holes in a thickness direction, including an oxidized film-forming step of forming an oxidized film by carrying out an oxidized film-forming treatment on a surface of the aluminum substrate having a thickness in a range of 5 ?m to 1,000 ?m and a through hole-forming step of forming through holes by carrying out an electrochemical dissolution treatment after the oxidized film-forming step.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: March 17, 2020
    Assignee: FUJIFILM Corporation
    Inventors: Atsushi Matsuura, Yuichi Kasuya, Junji Kawaguchi, Hisashi Hotta, Yoshinori Hotta, Hiroshi Komatsu, Hirokazu Sawada
  • Publication number: 20180302324
    Abstract: Effective data distribution without special hardware such as CAM. A unique Route ID in the network is used to determine the destinations for a sent packet. On creating the routing information for the Route ID, each node in the network creates an entry in its own forwarding table within the node. A linear memory offset in the table, called LookUp ID, is used to access the entry. By exchanging the LookUp ID with neighboring nodes and updating the forwarding table entry, the packet distribution path can be determined for the given Route ID. When a packet is sent for the given Route ID, each node updates the predetermined field in the packet with neighbor LookUp ID and sends it to the neighbor node, so the neighbor node can access its own entry as a regular memory access with the LookUp ID to determine where to forward the packet.
    Type: Application
    Filed: April 18, 2018
    Publication date: October 18, 2018
    Inventor: Atsushi Kasuya
  • Patent number: 8170028
    Abstract: A network device includes an input interface, at least one processing path and an output interface. The input interface receives data units on a plurality of streams and assigns a first sequence number to each of the received data units. The at least one processing path performs a route look-up for each of the data units, where the route look-up determines a routing destination for a respective data unit. The output interface assigns a second sequence number to each of the processed data units based on a number of memory references associated with the route look-up for each of the data units and re-orders the processed data units based on the second sequence number assigned to each of the processed data units.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: May 1, 2012
    Assignee: Juniper Networks, Inc.
    Inventors: Dennis C Ferguson, Hann-Hwan Ju, Atsushi Kasuya, Gerald Cheung, Devereaux C Chen
  • Patent number: 8117333
    Abstract: A network device includes at least one input interface, at least one processing path and at least one output interface. The at least one input interface receives data blocks from a plurality of streams in a first order. The at least one processing path processes each of the data blocks, the processing including performing one or more route look-ups for each of the data blocks. The at least one output interface re-orders the data blocks based on a number of the one or more route look-ups associated with each of the data blocks.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: February 14, 2012
    Assignee: Juniper Networks, Inc.
    Inventors: Junying James Yu, Dennis C. Ferguson, Hasan F. Ugurdag, Atsushi Kasuya
  • Publication number: 20100280898
    Abstract: A method for a personalized reward system, the method includes obtaining a reward list comprising one or more reward each associated with a corresponding reward point required for a corresponding reward redemption, obtaining a task list comprising one or more tasks each associated with a corresponding reward point that can be earned upon a corresponding task completion, receiving a input from a user indicating a task of the one or more tasks is completed, adding a corresponding reward point associate with the task to generate a cumulative reward point based on a first pre-determined criterion, comparing the cumulative reward point to the reward list based on a second first pre-determined criterion to generate a result, and notifying the user of a reward redemption based on the result.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 4, 2010
    Inventor: Atsushi Kasuya
  • Patent number: 7769962
    Abstract: A system and a method for thread creation where only copied threads share the same stack location for execution, so unrelated threads have individual stack space and can be executed concurrently in multi-processor system. Also, the copy operation of the stack frame is only necessary among the copied threads, so the speed of context switching among individual threads is fast. This operation can be a simple page table modification in the virtual memory management mechanism for further speed up.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: August 3, 2010
    Assignee: Jeda Technologies, Inc.
    Inventor: Atsushi Kasuya
  • Patent number: 7606826
    Abstract: Evaluation information of a temporal description is displayed by: structuring data structures into a logical tree structure that is representative of the hierarchy of the temporal expressions, with each tree node representing a temporal primitive operator, and a unique index assigned to each primitive; evaluating the temporal expression, and recording the evaluation trace information that contains the corresponding unique index to the primitive node, the evaluation time stamp, and other information of the evaluation; and selectively displaying an evaluation sequence of the selected result at any level, including from the top of the tree structure of the temporal evaluation in order to show the evaluation history of the selected result at a lower level of the expression tree, where the selection methods include a graphical interface on the screen to select a child expression at a given tree level.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: October 20, 2009
    Assignee: Jeda Technologies, Inc.
    Inventors: Chaoji Li, Atsushi Kasuya, Jianzhou Zhao, Baodong Yu
  • Patent number: 7586917
    Abstract: A network device includes an input interface, at least one processing path and an output interface. The input interface receives data units on a plurality of streams and assigns a first sequence number to each of the received data units. The at least one processing path performs a route look-up for each of the data units, where the route look-up determines a routing destination for a respective data unit. The output interface assigns a second sequence number to each of the processed data units based on a number of memory references associated with the route look-up for each of the data units and re-orders the processed data units based on the second sequence number assigned to each of the processed data units.
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: September 8, 2009
    Assignee: Juniper Networks, Inc.
    Inventors: Dennis C. Ferguson, Hann-Hwan Ju, Atsushi Kasuya, Gerald Cheung, Devereaux C. Chen
  • Publication number: 20080010432
    Abstract: A system and a method for thread creation where only copied threads share the same stack location for execution, so unrelated threads have individual stack space and can be executed concurrently in multi-processor system. Also, the copy operation of the stack frame is only necessary among the copied threads, so the speed of context switching among individual threads is fast. This operation can be a simple page table modification in the virtual memory management mechanism for further speed up.
    Type: Application
    Filed: July 10, 2007
    Publication date: January 10, 2008
    Applicant: JEDA Technologies
    Inventor: Atsushi Kasuya
  • Publication number: 20070136403
    Abstract: A system and method for thread management, including one or more smart pointers that can be identified while creating a copy of the stack, and incremented the reference counter within the smart pointer to reflect the copy operation.
    Type: Application
    Filed: December 12, 2005
    Publication date: June 14, 2007
    Inventor: Atsushi Kasuya
  • Publication number: 20070083548
    Abstract: The present invention discloses methods in structuring data structures into a logical tree structure that is representative the hierarchy of the temporal expressions, with each tree node represent a temporal primitive operator, and an unique index being assigned to each primitive. It further discloses methods for evaluating the temporal expression, and recording the evaluation trace information that contains the corresponding unique index to the primitive node, the evaluation time stamp, and other information of the evaluation; and methods for selectively displaying an evaluation sequence of the selected result at any level, including from the top of the tree structure of the temporal evaluation in order to show the evaluation history of the selected result at lower level of the expression tree, where the selection methods include a graphical interface on the screen to select a child expression at a given tree level.
    Type: Application
    Filed: December 4, 2006
    Publication date: April 12, 2007
    Inventors: Chaoji Li, Atsushi Kasuya, Jianzhou Zhao, Baodong Yu
  • Publication number: 20060277534
    Abstract: A translation module translates a temporal description into a temporal expression. The translation module is adapted to translate a temporal description in the form of an extended syntax or a preprocessing macro to the temporal expression. The temporal expression includes a native expression of a general purpose programming language. The temporal expression may also include one or more construct functions. A parsing module parses the temporal expression to generate a data structure that represents the temporal expression without evaluating the native expression. An evaluation module evaluates the data structure to execute the temporal expression including the native expression.
    Type: Application
    Filed: June 7, 2005
    Publication date: December 7, 2006
    Inventor: Atsushi Kasuya
  • Publication number: 20060271345
    Abstract: A circuit is tested using a device under test, a circuit simulator, and a circuit simulation verifier. Executing the verifier drives the simulator and collects trace information. This trace information enables the verifier to be executed backwards to a past execution point or clock cycle. The internal state of the verifier's execution is reconstructed at the past point. A state of verifier execution includes values of variables (including any ports or clocks) and an execution point (e.g., which code statement was last executed). A past state of execution can be determined by using trace information to modify the current state of execution. After a line of trace information has been processed, the “current” state of verifier execution becomes the previous state as modified based on the trace information.
    Type: Application
    Filed: May 18, 2005
    Publication date: November 30, 2006
    Inventor: Atsushi Kasuya
  • Patent number: 6077304
    Abstract: An electronic circuit verification system and method includes an HDL circuit simulator and a circuit simulation verifier that pass control back and forth between each other, and that cooperate so as to perform circuit verification tasks than would be very difficult to perform using only the HDL circuit simulator. The circuit simulation verifier executes a test bench so as to define operational correctness and/or performance criteria, including at least one Expect Event, each Expect Event comprising a combination of one or more signal values that are expected to occur during simulation, and a time frame during which the signal value combination is expected to occur. The circuit simulation verifier includes instructions for blocking execution of a thread of execution associated with the test bench until the earlier of the combination of one or more signal values occurring during simulation and the time frame expiring.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: June 20, 2000
    Assignee: Sun Microsystems, Inc.
    Inventor: Atsushi Kasuya
  • Patent number: 5905883
    Abstract: An electronic circuit verification system and method includes an HDL circuit simulator and a circuit simulation verifier that pass control back and forth between each other, and that cooperate so as to perform circuit verification tasks than would be very difficult to perform using only the HDL circuit simulator. The circuit simulation verifier is coupled to the HDL circuit simulator so as to control the HDL circuit simulator's operation, including specifying conditions under which the HDL circuit simulator is to stop simulation of a specified circuit and specifying input signal waveforms to be used by the HDL circuit simulator. The circuit simulation verifier receives signal waveforms generated by the HDL circuit simulator for specified watched signals. The circuit simulation verifier then determines whether predefined logical combinations of the watched signals meet specified operational correctness and/or performance criteria within specified time frames.
    Type: Grant
    Filed: April 15, 1996
    Date of Patent: May 18, 1999
    Assignee: Sun Microsystems, Inc.
    Inventor: Atsushi Kasuya