Abstract: A system and a method for thread creation where only copied threads share the same stack location for execution, so unrelated threads have individual stack space and can be executed concurrently in multi-processor system. Also, the copy operation of the stack frame is only necessary among the copied threads, so the speed of context switching among individual threads is fast. This operation can be a simple page table modification in the virtual memory management mechanism for further speed up.

Abstract: Evaluation information of a temporal description is displayed by: structuring data structures into a logical tree structure that is representative of the hierarchy of the temporal expressions, with each tree node representing a temporal primitive operator, and a unique index assigned to each primitive; evaluating the temporal expression, and recording the evaluation trace information that contains the corresponding unique index to the primitive node, the evaluation time stamp, and other information of the evaluation; and selectively displaying an evaluation sequence of the selected result at any level, including from the top of the tree structure of the temporal evaluation in order to show the evaluation history of the selected result at a lower level of the expression tree, where the selection methods include a graphical interface on the screen to select a child expression at a given tree level.

Abstract: A network device includes an input interface, at least one processing path and an output interface. The input interface receives data units on a plurality of streams and assigns a first sequence number to each of the received data units. The at least one processing path performs a route look-up for each of the data units, where the route look-up determines a routing destination for a respective data unit. The output interface assigns a second sequence number to each of the processed data units based on a number of memory references associated with the route look-up for each of the data units and re-orders the processed data units based on the second sequence number assigned to each of the processed data units.

Abstract: A system and a method for thread creation where only copied threads share the same stack location for execution, so unrelated threads have individual stack space and can be executed concurrently in multi-processor system. Also, the copy operation of the stack frame is only necessary among the copied threads, so the speed of context switching among individual threads is fast. This operation can be a simple page table modification in the virtual memory management mechanism for further speed up.

Abstract: A system and method for thread management, including one or more smart pointers that can be identified while creating a copy of the stack, and incremented the reference counter within the smart pointer to reflect the copy operation.

Abstract: The present invention discloses methods in structuring data structures into a logical tree structure that is representative the hierarchy of the temporal expressions, with each tree node represent a temporal primitive operator, and an unique index being assigned to each primitive. It further discloses methods for evaluating the temporal expression, and recording the evaluation trace information that contains the corresponding unique index to the primitive node, the evaluation time stamp, and other information of the evaluation; and methods for selectively displaying an evaluation sequence of the selected result at any level, including from the top of the tree structure of the temporal evaluation in order to show the evaluation history of the selected result at lower level of the expression tree, where the selection methods include a graphical interface on the screen to select a child expression at a given tree level.

Abstract: A translation module translates a temporal description into a temporal expression. The translation module is adapted to translate a temporal description in the form of an extended syntax or a preprocessing macro to the temporal expression. The temporal expression includes a native expression of a general purpose programming language. The temporal expression may also include one or more construct functions. A parsing module parses the temporal expression to generate a data structure that represents the temporal expression without evaluating the native expression. An evaluation module evaluates the data structure to execute the temporal expression including the native expression.

Abstract: A circuit is tested using a device under test, a circuit simulator, and a circuit simulation verifier. Executing the verifier drives the simulator and collects trace information. This trace information enables the verifier to be executed backwards to a past execution point or clock cycle. The internal state of the verifier's execution is reconstructed at the past point. A state of verifier execution includes values of variables (including any ports or clocks) and an execution point (e.g., which code statement was last executed). A past state of execution can be determined by using trace information to modify the current state of execution. After a line of trace information has been processed, the “current” state of verifier execution becomes the previous state as modified based on the trace information.

Abstract: An electronic circuit verification system and method includes an HDL circuit simulator and a circuit simulation verifier that pass control back and forth between each other, and that cooperate so as to perform circuit verification tasks than would be very difficult to perform using only the HDL circuit simulator. The circuit simulation verifier executes a test bench so as to define operational correctness and/or performance criteria, including at least one Expect Event, each Expect Event comprising a combination of one or more signal values that are expected to occur during simulation, and a time frame during which the signal value combination is expected to occur. The circuit simulation verifier includes instructions for blocking execution of a thread of execution associated with the test bench until the earlier of the combination of one or more signal values occurring during simulation and the time frame expiring.

Abstract: An electronic circuit verification system and method includes an HDL circuit simulator and a circuit simulation verifier that pass control back and forth between each other, and that cooperate so as to perform circuit verification tasks than would be very difficult to perform using only the HDL circuit simulator. The circuit simulation verifier is coupled to the HDL circuit simulator so as to control the HDL circuit simulator's operation, including specifying conditions under which the HDL circuit simulator is to stop simulation of a specified circuit and specifying input signal waveforms to be used by the HDL circuit simulator. The circuit simulation verifier receives signal waveforms generated by the HDL circuit simulator for specified watched signals. The circuit simulation verifier then determines whether predefined logical combinations of the watched signals meet specified operational correctness and/or performance criteria within specified time frames.