Abstract: A seat comprises a seat cushion pad (20) including an air flow passage (21), and a blower connected to the air flow passage (21). The seat cushion pad (20) comprises a pad body (100), and a cover member (200) disposed on an upper surface of the pad body (100) to form the air flow passage (21) between the pad body (100) and the cover member (200). The cover member (200) comprises a first cover member (210) disposed on the upper surface of the pad body (100), and a second cover member (220) disposed on an upper surface of the first cover member (210). The first cover member (210) is fixed to the pad body (100), and the second cover member (220) is fixed to the first cover member (210) and to the pad body (100).

Abstract: An exhaust gas purification device includes a pre-oxidation catalyst disposed in an exhaust gas passage and a muffler that is provided in such a manner as to surround the pre-oxidation catalyst, and discharges exhaust gas while reducing noise. The muffler has an inlet which is connected to an upstream side exhaust pipe and an outlet which is connected to a downstream side exhaust pipe. The exhaust gas purification device includes a downstream side purification device that is disposed in the exhaust gas passage, and accommodates a second oxidation catalyst and a particulate matter removing filter. The exhaust gas is discharged to the atmosphere after the exhaust gas flows through the downstream side purification device.

Abstract: An exhaust gas purification device includes a pre-oxidation catalyst disposed in an exhaust gas passage and a muffler that is provided in such a manner as to surround the pre-oxidation catalyst, and discharges exhaust gas while reducing noise. The muffler has an inlet which is connected to an upstream side exhaust pipe and an outlet which is connected to a downstream side exhaust pipe. The exhaust gas purification device includes a downstream side purification device that is disposed in the exhaust gas passage, and accommodates a second oxidation catalyst and a particulate matter removing filter. The exhaust gas is discharged to the atmosphere after the exhaust gas flows through the downstream side purification device.

Abstract: According to one embodiment, a semiconductor memory device includes a first electrode layer having a first area, a second area, and a connection area connecting the first area to the second area, and a plurality of semiconductor pillars extending in a first direction through the first electrode layer in the first area and the second area. The plurality of semiconductor pillars are arranged in an array in a second direction and in a third direction intersecting with the second direction, the second direction and the third direction being parallel to the surface of the first electrode layer, and the connection area has no semiconductor pillars disposed therein.

Abstract: According to one embodiment, a semiconductor memory device includes a first electrode layer having a first area, a second area, and a connection area connecting the first area to the second area, and a plurality of semiconductor pillars extending in a first direction through the first electrode layer in the first area and the second area. The plurality of semiconductor pillars are arranged in an array in a second direction and in a third direction intersecting with the second direction, the second direction and the third direction being parallel to the surface of the first electrode layer, and the connection area has no semiconductor pillars disposed therein.

Abstract: According to an embodiment, a semiconductor memory device comprises: a stacked body including control gate electrodes stacked upwardly of a substrate; a semiconductor layer facing the control gate electrodes; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The stacked body comprises: a first metal layer configuring the control gate electrode; a first barrier metal layer contacting an upper surface of this first metal layer; a first silicon nitride layer contacting an upper surface of this first barrier metal layer; a first inter-layer insulating layer contacting an upper surface of this first silicon nitride layer; a second barrier metal layer contacting a lower surface of the first metal layer; a second silicon nitride layer contacting a lower surface of this second barrier metal layer; and a second inter-layer insulating layer contacting a lower surface of this second silicon nitride layer.

Abstract: According to an embodiment, a semiconductor memory device comprises a substrate, a plurality of first conductive layers, a memory columnar body, a first semiconductor layer, a second semiconductor layer and a contact. The plurality of first conductive layers are stacked upwardly of the substrate. The memory columnar body extends in a first direction intersecting an upper surface of the substrate and a side surface of the memory columnar body is covered by the first conductive layers. The first semiconductor layer is connected to a lower end of the memory columnar body and extends in a second direction intersecting the first direction. The second conductive layer is provided between the first semiconductor layer and the first conductive layers. The second conductive layer is connected to the memory columnar body and extending in the second direction. The contact is connected to the second conductive layer and extends in the first direction.

Abstract: According to an embodiment, a semiconductor memory device comprises: a stacked body including control gate electrodes stacked upwardly of a substrate; a semiconductor layer facing the control gate electrodes; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The stacked body comprises: a first metal layer configuring the control gate electrode; a first barrier metal layer contacting an upper surface of this first metal layer; a first silicon nitride layer contacting an upper surface of this first barrier metal layer; a first inter-layer insulating layer contacting an upper surface of this first silicon nitride layer; a second barrier metal layer contacting a lower surface of the first metal layer; a second silicon nitride layer contacting a lower surface of this second barrier metal layer; and a second inter-layer insulating layer contacting a lower surface of this second silicon nitride layer.

Abstract: According to an embodiment, a semiconductor memory device comprises a substrate, a plurality of first conductive layers, a memory columnar body, a first semiconductor layer, a second semiconductor layer and a contact. The plurality of first conductive layers are stacked upwardly of the substrate. The memory columnar body extends in a first direction intersecting an upper surface of the substrate and a side surface of the memory columnar body is covered by the first conductive layers. The first semiconductor layer is connected to a lower end of the memory columnar body and extends in a second direction intersecting the first direction. The second conductive layer is provided between the first semiconductor layer and the first conductive layers. The second conductive layer is connected to the memory columnar body and extending in the second direction. The contact is connected to the second conductive layer and extends in the first direction.

Abstract: In an oil pan inner tank valve structure, a disc-shaped float valve is arranged below a valve port that provides fluid communication between the inside and outside of a bottom wall of an inner tank, and a lower cover is arranged below the float valve. In addition, a center recess is depressed at a lower surface center of the float valve, and a lateral movement restricting pin is upright from the lower cover and is constantly engaged with the center recess by recess/protrusion engagement. The lower cover restricts a vertically movable range of the float valve. In addition, the lateral movement restricting pin restricts lateral movement of the float valve so that a top portion of an upper surface bulged portion vertically constantly faces an area inside a valve seat.

Abstract: According to an aspect of the invention, a first insulating layer is buried in a first trench provided in at least one of an interstice between first and second semiconductor pillars, a side surface portion of the first semiconductor pillar opposed to the second semiconductor pillar, and a side surface portion of the second semiconductor pillar opposed to the first semiconductor pillar. A first trench penetrates each stack from an uppermost portion of the stack to a first conductive layer in a lowermost portion of the stack. The first trench is arranged away from a first connection portion. Each of the first conductive layers in contact with the first insulating layer includes a silicide layer.

Abstract: According to an embodiment, in a method of fabricating a nonvolatile semiconductor memory device, second trenches penetrating the first and second conductive layers above the first trenches are formed to reach the stack, and a second insulating layer is formed on the second trenches and the first insulating layer so as to fill the second trenches. A part of the second insulating layer in a first region extending in a direction orthogonal to a direction that the first and second semiconductor pillars extend in a plane parallel to the back gate layer is removed while a part of the second insulating layer in a second region adjacent to the first region is left. The first sacrificial layer is selectively removed, and the first conductive layers and second conductive layers exposed in the first and second trenches are silicidized.

Abstract: According to an embodiment, in a method of fabricating a nonvolatile semiconductor memory device, second trenches penetrating the first and second conductive layers above the first trenches are formed to reach the stack, and a second insulating layer is formed on the second trenches and the first insulating layer so as to fill the second trenches. A part of the second insulating layer in a first region extending in a direction orthogonal to a direction that the first and second semiconductor pillars extend in a plane parallel to the back gate layer is removed while a part of the second insulating layer in a second region adjacent to the first region is left. The first sacrificial layer is selectively removed, and the first conductive layers and second conductive layers exposed in the first and second trenches are silicidized.

Abstract: According to an aspect of the invention, a first insulating layer is buried in a first trench provided in at least one of an interstice between first and second semiconductor pillars, a side surface portion of the first semiconductor pillar opposed to the second semiconductor pillar, and a side surface portion of the second semiconductor pillar opposed to the first semiconductor pillar. A first trench penetrates each stack from an uppermost portion of the stack to a first conductive layer in a lowermost portion of the stack. The first trench is arranged away from a first connection portion. Each of the first conductive layers in contact with the first insulating layer includes a silicide layer.

Abstract: According to one embodiment, a method for manufacturing a nonvolatile semiconductor storage device includes; forming a first and a second stacked bodies; forming a through hole penetrating through the first stacked body, a second portion communicating with the first portion and penetrating through a select gate, and a third portion communicating with the second portion and penetrating through a second insulating layer; forming a memory film, a gate insulating film, and a channel body; forming a third insulating layer inside the channel body; forming a first embedded portion above a boundary portion inside the third portion; exposing the channel body by removing part of the first embedded portion and part of the third insulating layer in the third portion; and embedding a second embedded portion including silicon having higher impurity concentration than the first embedded portion above the first embedded portion inside the third portion.

Abstract: In an oil pan inner tank valve structure, a disc-shaped float valve is arranged below a valve port that provides fluid communication between the inside and outside of a bottom wall of an inner tank, and a lower cover is arranged below the float valve. In addition, a center recess is depressed at a lower surface center of the float valve, and a lateral movement restricting pin is upright from the lower cover and is constantly engaged with the center recess by recess/protrusion engagement. The lower cover restricts a vertically movable range of the float valve. In addition, the lateral movement restricting pin restricts lateral movement of the float valve so that a top portion of an upper surface bulged portion vertically constantly faces an area inside a valve seat.

Abstract: According to one embodiment, a method for manufacturing a nonvolatile semiconductor storage device includes; forming a first and a second stacked bodies; forming a through hole penetrating through the first stacked body, a second portion communicating with the first portion and penetrating through a select gate, and a third portion communicating with the second portion and penetrating through a second insulating layer; forming a memory film, a gate insulating film, and a channel body; forming a third insulating layer inside the channel body; forming a first embedded portion above a boundary portion inside the third portion; exposing the channel body by removing part of the first embedded portion and part of the third insulating layer in the third portion; and embedding a second embedded portion including silicon having higher impurity concentration than the first embedded portion above the first embedded portion inside the third portion.

Abstract: Provided are a high-quality graphene or graphite thin film compatible with a large surface area, a manufacturing method that can epitaxially form the graphene or graphite thin film on a Si substrate, a thin film structure, and an electronic device having the same. The present invention provides a graphene or graphite thin film formed on a cubic SiC crystal thin film having a (111) orientation formed on a Si substrate, the cubic SiC crystal thin film being used as a base material. Additionally, the development of ultra-high-speed devices that support next-generation high-speed communication services can be advanced by means of an electronic device having a graphene or graphite thin film structure grown as a crystal on a substrate.

Abstract: A semiconductor memory device includes a plurality of transistors on a semiconductor substrate; a first interlayer dielectric film on the transistors; a plurality of ferroelectric capacitors on the first interlayer dielectric film; a first hydrogen barrier film covering an upper surface and a side surface of each of the ferroelectric capacitors; a second interlayer dielectric film above the ferroelectric capacitors, the second interlayer dielectric film being buried to have a void or hole between two adjacent ferroelectric capacitors out of the ferroelectric capacitors; a cover dielectric film covering the second interlayer dielectric film to close an opening of the void or hole; and a second hydrogen barrier film covering the cover dielectric film.

Abstract: A positioning information transmitter transmits a positioning identifier instead of directly transmitting position information. A positioning information management server stores and manages the positioning identifier and the position information while correlating them with each other. In response to a position information request with a positioning identifier, the positioning information management server converts the positioning identifier into position information according to the aforementioned correlation. Furthermore, the positioning information management server updates the positioning identifier to be transmitted from the positioning information transmitter in a certain time by using predetermined means.