Patents by Inventor Atsushi Kurokawa

Atsushi Kurokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10168642
    Abstract: A developing device includes upper and lower developer containing portions to contain developer, arranged in a vertical direction, a first developer conveyor to convey developer in the upper developer containing portion to a first side in an axial direction of the first developer conveyor, a second developer conveyor to convey developer in the lower developer containing portion to a second side opposite the first side, a developer-lifting area in which the developer is lifted from the lower developer containing portion to the upper developer containing portion, a first lifting area gear to rotate the first developer conveyor, a second lifting area gear to rotate the second developer conveyor, and a lifting area input gear to input a driving force to the developing device. The lifting area input gear is coupled to the first lifting area gear and coupled via the first lifting area gear via to the second lifting area gear.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: January 1, 2019
    Assignee: Ricoh Company, Ltd.
    Inventors: Tatsuya Ohhira, Masayuki Yamane, Keiichi Yoshida, Atsushi Kurokawa, Toshiki Hayashi, Yuuki Tsuchiya
  • Patent number: 10163749
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the semiconductor element, and a passivation film that protects the semiconductor element. The passivation film is formed by alternately stacking a first insulation film that has larger tensile stress and a second insulation film that has smaller tensile stress. Each of the first insulation film and the second insulation film is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film. The passivation film as a whole generates tensile stress.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: December 25, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masayuki Aoike, Atsushi Kurokawa, Atsushi Kobayashi
  • Patent number: 10157812
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the semiconductor element, and a passivation film that protects the semiconductor element. The passivation film is formed by alternately stacking a first insulation film that generates compressive stress and has low density and a second insulation film that generates compressive stress and has high density. The first insulation film is disposed in a lowest layer of the passivation film, the lowest layer being nearest to the semiconductor substrate. Each of the first insulation film and the second insulation film is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: December 18, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masayuki Aoike, Atsushi Kurokawa, Atsushi Kobayashi
  • Patent number: 10147809
    Abstract: In a bipolar transistor, a collector layer includes three semiconductor layers: an n-type GaAs layer (Si concentration: about 5×1015 cm?3, thickness: about 350 nm), a p-type GaAs layer (C concentration: about 4.5×1015 cm?3, thickness: about 100 nm, sheet concentration: 4.5×1010 cm?2), and an n-type GaAs layer Si concentration: about 5×1015 cm?3, thickness: about 500 nm. The sheet concentration of the p-type GaAs layer is set to less than 1×1011 cm?2.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: December 4, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Atsushi Kurokawa, Tsunekazu Saimei
  • Patent number: 10114334
    Abstract: A developing device includes a developer bearer, a casing defining an upper compartment to contain the developer and a lower compartment disposed lower than the upper compartment, to contain the developer, and a first conveyor and a second conveyor disposed in the upper compartment and the lower compartment, respectively, to convey the developer in a longitudinal direction of the developer bearer and circulate the developer between the upper compartment and the lower compartment through a first communicating opening, through which the developer is conveyed upward, and a second communicating opening. A developer-lifting range of the upper compartment, which opposes the first communicating opening, is larger in volume than a developer-lifting range of the lower compartment. One of the upper compartment and the lower compartment is disposed adjacent to the developer bearer to supply the developer to the developer bearer.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: October 30, 2018
    Assignee: Ricoh Company, Ltd.
    Inventors: Tatsuya Ohhira, Masayuki Yamane, Keiichi Yoshida, Atsushi Kurokawa, Toshiki Hayashi, Yuuki Tsuchiya
  • Publication number: 20180247895
    Abstract: A semiconductor device includes electrodes which contain Au and which are placed above conductive layers in a region adjacent to stacked insulating films and also includes base layers which are composed of compositionally modulated layers and which are placed between the electrodes and the conductive layers. The base layers include lateral end sections composed of single layers projecting from lateral end sections of the electrodes in the direction of the interlayer interface between the insulating films; sections which are located under the electrodes and of which a major compositional component is Ti or Ti and W; and projecting sections which project from under the electrodes in the direction of the interlayer interface between the insulating films and of which compositional components are compositionally modulated to Ti and O, to Ti, O, and N, or to Ti, W, O, and N.
    Type: Application
    Filed: February 23, 2018
    Publication date: August 30, 2018
    Inventors: Yuichi SANO, Atsushi KUROKAWA, Kazuya KOBAYASHI
  • Publication number: 20180248023
    Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.
    Type: Application
    Filed: April 19, 2018
    Publication date: August 30, 2018
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari UMEMOTO, Shigeki KOYA, Atsushi KUROKAWA
  • Publication number: 20180175181
    Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.
    Type: Application
    Filed: September 1, 2017
    Publication date: June 21, 2018
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasunari UMEMOTO, Shigeki KOYA, Atsushi KUROKAWA
  • Patent number: 10002950
    Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: June 19, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Shigeki Koya, Atsushi Kurokawa
  • Publication number: 20180143568
    Abstract: A developing device includes upper and lower developer containing portions to contain developer, arranged in a vertical direction, a first developer conveyor to convey developer in the upper developer containing portion to a first side in an axial direction of the first developer conveyor, a second developer conveyor to convey developer in the lower developer containing portion to a second side opposite the first side, a developer-lifting area in which the developer is lifted from the lower developer containing portion to the upper developer containing portion, a first lifting area gear to rotate the first developer conveyor, a second lifting area gear to rotate the second developer conveyor, and a lifting area input gear to input a driving force to the developing device. The lifting area input gear is coupled to the first lifting area gear and coupled via the first lifting area gear via to the second lifting area gear.
    Type: Application
    Filed: September 28, 2017
    Publication date: May 24, 2018
    Applicant: Ricoh Company, Ltd.
    Inventors: Tatsuya Ohhira, Masayuki Yamane, Keiichi Yoshida, Atsushi Kurokawa, Toshiki Hayashi, Yuuki Tsuchiya
  • Publication number: 20180136586
    Abstract: A developing device includes a casing to contain developer, a developer bearer, an upper and lower developer conveyors to convey the developer to one side in an axial direction of rotation shafts thereof, a communicating portion disposed on a first end side on which an input gear is disposed, to fall the developer from the upper developer conveyor to the lower developer conveyor, bearings to receive end portions the upper and lower developer conveyors, and first and second end seals to seal gaps in the bearings on the upper and lower developer conveyors, respectively. The first end seals and the second end are disposed on the first end side and a second end side, respectively. A sliding friction between the rotation shaft and at least one of the first end seals is smaller than a sliding friction between the rotation shaft and the second end seal.
    Type: Application
    Filed: September 6, 2017
    Publication date: May 17, 2018
    Applicant: Ricoh Company, Ltd.
    Inventors: Yuuki TSUCHIYA, Masayuki YAMANE, Keiichi YOSHIDA, Atsushi KUROKAWA, Toshiki HAYASHI, Tatsuya OHHIRA
  • Publication number: 20180108588
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the semiconductor element, and a passivation film that protects the semiconductor element. The passivation film is formed by alternately stacking a first insulation film that has larger tensile stress and a second insulation film that has smaller tensile stress. Each of the first insulation film and the second insulation film is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film. The passivation film as a whole generates tensile stress.
    Type: Application
    Filed: October 16, 2017
    Publication date: April 19, 2018
    Inventors: Masayuki Aoike, Atsushi Kurokawa, Atsushi Kobayashi
  • Publication number: 20180108589
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the semiconductor element, and a passivation film that protects the semiconductor element. The passivation film is formed by alternately stacking a first insulation film that generates compressive stress and has low density and a second insulation film that generates compressive stress and has high density. The first insulation film is disposed in a lowest layer of the passivation film, the lowest layer being nearest to the semiconductor substrate. Each of the first insulation film and the second insulation film is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film.
    Type: Application
    Filed: October 16, 2017
    Publication date: April 19, 2018
    Inventors: Masayuki Aoike, Atsushi Kurokawa, Atsushi Kobayashi
  • Patent number: 9864297
    Abstract: A developing device includes a developer bearer, a magnetic field generator, a casing having an opening, a developer conveyor to rotate inside a developer containing compartment below the developer bearer, and a developer regulator. A side wall of the casing defines a bottom end of the opening, and the developer regulator is disposed on the side wall. The side wall includes an upper end face facing the developer bearer below an axis of the developer bearer and a curved inner face along an orbit of rotation of the developer conveyor, extending from below the developer conveyor toward the upper end face. On a virtual plane perpendicular to the axis of the developer bearer, an intersection between a tangent line to an upper end of the curved inner face and the surface of the developer bearer is in a range from a tangential magnetic-flux peak and a closest approach point.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 9, 2018
    Assignee: Ricoh Company, Ltd.
    Inventors: Tatsuya Ohhira, Atsushi Kurokawa, Masayuki Yamane, Keiichi Yoshida, Toshiki Hayashi, Sayuri Katoh
  • Patent number: 9862167
    Abstract: A laminated body includes: an antireflection film; and a protection film bonded onto the antireflection film. The adhesive layer is a layer with a material formed by cross-linking, with a cross-linking agent (B), and a (meth)acrylic acid ester copolymer. The (meth)acrylic acid ester copolymer (A) is a copolymer formed by polymerizing monomer components including, in relation to the total amount of the monomer components set at 100% by mass, 70 to 98% by mass of a (meth)acrylic acid alkyl ester monomer (a) including a noncyclic alkyl group containing 4 to 9 carbon atoms, 1.5 to 25% by mass of a (meth)acrylic acid ester monomer (b) containing an aliphatic ring, and 0.5 to 5% by mass of a (meth)acrylic-based monomer (c) containing a functional group exhibiting reactivity with the cross-linking agent (B). The area proportion of the components each having a molecular weight of 100,000 or less, is less than 3.0%.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: January 9, 2018
    Assignees: SHARP KABUSHIKI KAISHA, LINTEC CORPORATION
    Inventors: Tokio Taguchi, Atsushi Kurokawa, Takayuki Arai, Satoru Shoshi
  • Publication number: 20170293257
    Abstract: A developing device includes a developer bearer, a casing defining an upper compartment to contain the developer and a lower compartment disposed lower than the upper compartment, to contain the developer, and a first conveyor and a second conveyor disposed in the upper compartment and the lower compartment, respectively, to convey the developer in a longitudinal direction of the developer bearer and circulate the developer between the upper compartment and the lower compartment through a first communicating opening, through which the developer is conveyed upward, and a second communicating opening. A developer-lifting range of the upper compartment, which opposes the first communicating opening, is larger in volume than a developer-lifting range of the lower compartment. One of the upper compartment and the lower compartment is disposed adjacent to the developer bearer to supply the developer to the developer bearer.
    Type: Application
    Filed: March 23, 2017
    Publication date: October 12, 2017
    Inventors: Tatsuya OHHIRA, Masayuki YAMANE, Keiichi YOSHIDA, Atsushi KUROKAWA, Toshiki HAYASHI, Yuuki TSUCHIYA
  • Publication number: 20170090342
    Abstract: A developing device includes a developer bearer, a magnetic field generator, a easing having an opening, a developer conveyor to rotate inside a developer containing compartment below the developer bearer, and a developer regulator. A side wall of the casing defines a bottom end of the opening, and the developer regulator is disposed on the side wall. The side wall includes an upper end face facing the developer bearer below an axis of the developer bearer and a curved inner face along an orbit of rotation of the developer conveyor, extending from below the developer conveyor toward the upper end face. On a virtual plane perpendicular to the axis of the developer bearer, an intersection between a tangent line to an upper end of the curved inner face and the surface of the developer bearer is in a range from a tangential magnetic-flux peak and a closest approach point.
    Type: Application
    Filed: September 30, 2016
    Publication date: March 30, 2017
    Inventors: Tatsuya OHHIRA, Atsushi Kurokawa, Masayuki Yamane, Keiichi Yoshida, Toshiki Hayashi
  • Patent number: 9397204
    Abstract: A heterojunction bipolar transistor includes a collector layer composed of a semiconductor containing GaAs as a main component; a base layer including a first base layer and a second base layer the first base layer forming a heterojunction with the collector layer and being composed of a semiconductor containing a material as a main component, the material being lattice-mismatched to the main component of the collector layer, the first base layer having a film thickness less than a critical thickness at which a misfit dislocation is introduced, the second base layer being joined to the first base layer and composed of a semiconductor containing a material as a main component, and the material being lattice-matched to the main component of the collector layer; and an emitter layer that forms a heterojunction with the second base layer.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: July 19, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Atsushi Kurokawa
  • Patent number: 9362268
    Abstract: In a high-frequency circuit, it is necessary to provide galvanic blocking between active elements such as transistors and between an active element and an external terminal, and thus MIM capacitors or the like are used frequently. A MIM capacitor coupled to an external terminal is easily affected by static electricity from outside and causes a problem of electro-static breakdown or the like. In a MIM capacitor formed over a semi-insulating compound semiconductor substrate, a first electrode thereof is coupled to an external pad and to the semi-insulating compound semiconductor substrate, and a second electrode thereof is coupled to the semi-insulating compound semiconductor substrate.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: June 7, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Atsushi Kurokawa, Shinya Osakabe
  • Publication number: 20160133732
    Abstract: In a bipolar transistor, a collector layer includes three semiconductor layers: an n-type GaAs layer (Si concentration: about 5×1015 cm?3, thickness: about 350 nm), a p-type GaAs layer (C concentration: about 4.5×1015 cm?3, thickness: about 100 nm, sheet concentration: 4.5×1010 cm?2), and an n-type GaAs layer Si concentration: about 5×1015 cm?3, thickness: about 500 nm. The sheet concentration of the p-type GaAs layer is set to less than 1×1011 cm?2.
    Type: Application
    Filed: January 5, 2016
    Publication date: May 12, 2016
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasunari UMEMOTO, Atsushi KUROKAWA, Tsunekazu SAIMEI