Abstract: A timing adjustment circuit includes a voltage-controlled delay line, a phase detector, a control voltage generation circuit, and a startup circuit. The voltage-controlled delay line receives an input clock signal and generates multi-phase clocks, a delay amount of each of the multi-phase clocks is changed according to a control voltage. The phase detector detects a phase difference between a first clock and a second clock, the first clock is a reference, the second clock is generated from the voltage-controlled delay line. The control voltage generation circuit generates the control voltage on the basis of the detected phase difference. The startup circuit operates for a certain period after activation, and continuously changes the control voltage between a first voltage and a second voltage.

Abstract: An ADPLL includes a digital controlled oscillator, a first counter counting a number of clocks from the digital controlled oscillator, a second counter to count a multiplication number representing a number of the clocks in a reference clock, a TDC detecting a delayed amount of a phase of the clocks against a phase of the reference clock, an adder adding the delayed amount to a difference between the multiplication number and the number of clocks, a slew rate setting part setting a slew rate of the clocks, an ADC receiving the clocks to which the slew rate is set, a switching part switching between an output of the adder and an output of the ADC, and a controller controlling the slew rate by shifting a phase of the clocks to set a slew rate while the ADLL is locked by utilizing the TDC.

Abstract: A timing adjustment circuit includes a voltage-controlled delay line, a phase detector, a control voltage generation circuit, and a startup circuit. The voltage-controlled delay line receives an input clock signal and generates multi-phase clocks, a delay amount of each of the multi-phase clocks is changed according to a control voltage. The phase detector detects a phase difference between a first clock and a second clock, the first clock is a reference, the second clock is generated from the voltage-controlled delay line. The control voltage generation circuit generates the control voltage on the basis of the detected phase difference. The startup circuit operates for a certain period after activation, and continuously changes the control voltage between a first voltage and a second voltage.

Abstract: A first switching unit configured to switch a first state for inputting a first clock signal input from a first input terminal, and a second state for inputting an output signal of a second delay element, to a first delay element. A second switching unit configured to switch a first state for inputting a second clock signal input from a second input terminal, and a second state for inputting an output signal of a first delay element, to a second delay element. After the two clock signals are respectively taken in the first delay elements and the second delay elements by putting the first and second switching units into the first state, the control unit puts the first and second switching units into the second state. An output unit outputs a phase difference obtained by decoding values stored in FFs in the second state.

Abstract: A first switching unit configured to switch a first state for inputting a first clock signal input from a first input terminal, and a second state for inputting an output signal of a second delay element, to a first delay element. A second switching unit configured to switch a first state for inputting a second clock signal input from a second input terminal, and a second state for inputting an output signal of a first delay element, to a second delay element. After the two clock signals are respectively taken in the first delay elements and the second delay elements by putting the first and second switching units into the first state, the control unit puts the first and second switching units into the second state. An output unit outputs a phase difference obtained by decoding values stored in FFs in the second state.

Abstract: A clock generating circuit includes: a counter that counts a number of pulses of an oscillation clock signal existed within one cycle of a reference clock signal; a first time-to-digital converter that generates a plurality of phases of first clock signals by delaying the oscillation clock signal; a second time-to-digital converter that generates a plurality of phases of second clock signals by delaying the oscillation clock signal by a short delay time; a third time-to-digital converter that generates a plurality of phases of third clock signals by delaying the delayed first clock signal; a delay control unit that outputs a delay control signal based on a difference between a cycle of the oscillation clock signal and a target cycle; and an oscillator that generates, based on a cycle of the reference clock signal, the oscillation clock signal whose cycle is 1/m of the cycle of the reference clock signal.

Abstract: An ADPLL includes a digital controlled oscillator, a first counter counting a number of clocks from the digital controlled oscillator, a second counter to count a multiplication number representing a number of the clocks in a reference clock, a TDC detecting a delayed amount of a phase of the clocks against a phase of the reference clock, an adder adding the delayed amount to a difference between the multiplication number and the number of clocks, a slew rate setting part setting a slew rate of the clocks, an ADC receiving the clocks to which the slew rate is set, a switching part switching between an output of the adder and an output of the ADC, and a controller controlling the slew rate by shifting a phase of the clocks to set a slew rate while the ADLL is locked by utilizing the TDC.

Abstract: A TDC circuit include: a first delay circuit having first inverting delay devices connected to form a loop, the first inverting delay devices outputting a inverted signal according to an input signal after a first signal delay period; a second delay circuit having second inverting delay devices connected to form a loop, the second inverting delay according to an input signal after a second signal delay period different from the first signal delay period; first flip-flop circuits that latch the logical values of third pulse signals including the first pulse signal output from the first inverting delay devices based on fourth pulse signals including the second pulse signal or pulse signals; a first counter that counts the third pulse signal; a second counter that counts the fourth pulse signal; and a detection result output circuit that stores the count from the first counter and the count from the second counter.

Abstract: This method for forming ventilation holes in an electrode plate includes: a roughening step of roughening a surface of an electrode plate for a plasma processing apparatus such that a center line average roughness Ra becomes in a range of 0.2 ?m to 30 ?m; and a ventilation hole forming step of irradiating a laser beam having a wavelength within a range of 200 nm to 600 nm on a roughened surface of the electrode plate so as to form ventilation holes in the electrode plate which pass through the electrode plate in a thickness direction, wherein in the ventilation hole forming step, a focus spot of the laser light is swirled along a planar direction of the electrode plate so as to form a circular irradiation area, and while moving the irradiation area along a planar direction of the electrode plate in a circular movement, the focus spot of the laser light is shifted in a thickness direction of the electrode plate.

Abstract: A clock generating circuit includes: a counter that counts a number of pulses of an oscillation clock signal existed within one cycle of a reference clock signal; a first time-to-digital converter that generates a plurality of phases of first clock signals by delaying the oscillation clock signal; a second time-to-digital converter that generates a plurality of phases of second clock signals by delaying the oscillation clock signal by a short delay time; a third time-to-digital converter that generates a plurality of phases of third clock signals by delaying the delayed first clock signal; a delay control unit that outputs a delay control signal based on a difference between a cycle of the oscillation clock signal and a target cycle; and an oscillator that generates, based on a cycle of the reference clock signal, the oscillation clock signal whose cycle is 1/m of the cycle of the reference clock signal.

Abstract: A clock generator includes a digitally controlled oscillator configured to generate an output clock having a frequency depending on an input code; a phase comparison section configured to output a phase difference signal by comparing a reference phase with a phase of the output clock, the reference phase being based on an input clock and a predetermined frequency multiplication number; a low-pass filter configured to provide the input code for the digitally controlled oscillator by filtering the phase difference signal; a waveform generating section configured to generate a predetermined spread spectrum wave, the predetermined spread spectrum wave being to be added with both of the frequency multiplication number and the input code; and a detection/compensation section configured to compensate the input code so that the phase difference is reduced, the phase difference being detected from the phase difference signal.

Abstract: A clock generator includes a digitally controlled oscillator configured to generate an output clock haying a frequency depending on an input code; phase comparison section configured to output a phase differences signal by comparing a reference phase with a phase of the output clock, the reference phase being based on an input clock and a predetermined frequency multiplication number; low-pass filter configured to provide the input code for the digitally controlled oscillator by filtering the phase difference signal; a waveform generating section configured to generate a predetermined spread spectrum wave, the predetermined spread spectrum wave being to be added with both of the frequency multiplication number and the input code; and a detection/compensation section configured to compensate the input code so that the phase difference is reduced, the phase difference being detected from the phase difference signal.

Abstract: Disclosed are a method for early, sensitively and reliably detecting and distinguishing intrahepatic cholangiocarcinoma in a malignant tumor occurring primarily in the liver in a simple way, and a kit thereof. In the method, a glycan biomarker consisting of a lectin WFA (Wisteria floribunda Agglutinin)-binding glycoprotein derived from intrahepatic cholangiocarcinoma is used as a cancer marker to detect intrahepatic cholangiocarcinoma by detecting the cancer marker in a test specimen. The method for detecting intrahepatic cholangiocarcinoma can clearly differentiate intrahepatic cholangiocarcinoma from hepatocellular carcinoma and enables early detection and determination with a performance clinically acceptable in terms of applicability, sensitivity and precision.

Abstract: A PLL circuit includes: a first counter to accumulate a frequency command word in response to a reference clock signal and to generate a first counted value; a second counter to count an output clock signal and generate a second counted value; a time measuring circuit to measure an interval between a transition edge of the reference clock signal and a transition edge of the output clock signal to output a third counted value; a phase difference normalizing circuit to multiply the third counted value by a normalizing coefficient to generate a first phase difference; an operating circuit to subtract a value obtained by subtracting the first phase difference from the second counted value from the first counted value to generate a phase difference signal; and an oscillator to change a frequency of the output clock signal based on the phase difference signal.

Abstract: This method for forming ventilation holes in an electrode plate includes: a roughening step of roughening a surface of an electrode plate for a plasma processing apparatus such that a center line average roughness Ra becomes in a range of 0.2 ?m to 30 ?m; and a ventilation hole forming step of irradiating a laser beam having a wavelength within a range of 200 nm to 600 nm on a roughened surface of the electrode plate so as to form ventilation holes in the electrode plate which pass through the electrode plate in a thickness direction, wherein in the ventilation hole forming step, a focus spot of the laser light is swirled along a planar direction of the electrode plate so as to form a circular irradiation area, and while moving the irradiation area along a planar direction of the electrode plate in a circular movement, the focus spot of the laser light is shifted in a thickness direction of the electrode plate.

Abstract: A TDC circuit include: a first delay circuit having first inverting delay devices connected to form a loop, the first inverting delay devices outputting a inverted signal according to an input signal after a first signal delay period; a second delay circuit having second inverting delay devices connected to form a loop, the second inverting delay according to an input signal after a second signal delay period different from the first signal delay period; first flip-flop circuits that latch the logical values of third pulse signals including the first pulse signal output from the first inverting delay devices based on fourth pulse signals including the second pulse signal or pulse signals; a first counter that counts the third pulse signal; a second counter that counts the fourth pulse signal; and a detection result output circuit that stores the count from the first counter and the count from the second counter.

Abstract: Disclosed are a method for early, sensitively and reliably detecting and distinguishing intrahepatic cholangiocarcinoma in a malignant tumor occurring primarily in the liver in a simple way, and a kit therefor. In the method, a glycan biomarker consisting of a lectin WFA (Wisteria floribunda Agglutinin)-binding glycoprotein derived from intrahepatic cholangiocarcinoma is used as a cancer marker to detect intrahepatic cholangiocarcinoma by detecting the cancer marker in a test specimen. The method for detecting intrahepatic cholangiocarcinoma can clearly differentiate intrahepatic cholangiocarcinoma from hepatocellular carcinoma and enables early detection and determination with a performance clinically acceptable in terms of applicability, sensitivity and precision.

Abstract: A PLL circuit includes: a first counter to accumulate a frequency command word in response to a reference clock signal and to generate a first counted value; a second counter to count an output clock signal and generate a second counted value; a time measuring circuit to measure an interval between a transition edge of the reference clock signal and a transition edge of the output clock signal to output a third counted value; a phase difference normalizing circuit to multiply the third counted value by a normalizing coefficient to generate a first phase difference; an operating circuit to subtract a value obtained by subtracting the first phase difference from the second counted value from the first counted value to generate a phase difference signal; and an oscillator to change a frequency of the output clock signal based on the phase difference signal.

Abstract: A PLL circuit has a phase comparator to receive an input signal and a feedback signal, a charge pump controlled by an output of the phase comparator, a lowpass filter part to receive an output of the charge pump, a current controlled oscillator controlled by an output of the lowpass filter part, and a frequency divider to frequency-divide an output of the current controlled oscillator and to output the feedback signal. The lowpass filter part has an amplifier to receive the output of the charge pump and a reference voltage, and a circuit part including capacitors and resistors to receive the output of the charge pump and an output of the amplifier.

Abstract: A semiconductor device includes a first analog circuit (53) adapted to a first performance, and a second analog circuit (55) realizing a second performance higher than the first performance by cooperating with the first analog circuit. It becomes possible to switch circuit characteristics appropriately in accordance with a requested performance while suppressing an increase of a circuit scale, by operating the first analog circuit and interrupting a power supply to the second analog circuit when the first performance is requested, and by operating the first analog circuit and the second analog circuit together when the second performance is requested to thereby share the first analog circuit.