Abstract: According to one embodiment, a distance measuring apparatus includes a processing circuit and a memory. The processing circuit generates a distance image by measuring distances to an obstacle by using the time until the emitted light is reflected from the obstacle and returned as reflected light. The processing circuit generates an intensity image by measuring the intensity of the reflected light or the intensity of the environmental light. The memory stores a learned model for generating a denoise image, in which noise of the distance image is reduced, based on the distance image and the intensity image.

Abstract: A light-emitting element layer 10 includes: an n-type contact layer 11; a first light-emitting layer 12; a tunnel junction layer 13; a second light-emitting layer 14; and a p-type contact layer 15 laminated in this order. The first light-emitting layer 12 and the second light-emitting layer 14 emit light of the same wavelength. The tunnel junction layer 13 includes: a p-type tunnel layer 131 made of AlGaAs containing p-type impurities (C); and an n-type tunnel layer 133 made of GaInP containing n-type impurities (Te). A highly n-type impurities-doped layer 132 having a higher concentration of n-type impurities than the n-type tunnel layer 133 is arranged between the p-type tunnel layer 131 and the n-type tunnel layer 133.

Abstract: A light-emitting element layer (10) includes: an n-type contact layer (11); a first light-emitting layer (12); a tunnel junction layer (13); a second light-emitting layer (14); and a p-type contact layer (15) laminated in this order. The first light-emitting layer (12) and the second light-emitting layer (14) emit light of the same wavelength. The tunnel junction layer (13) includes: a p-type tunnel layer (131) made of AlGaAs containing p-type impurities (C); and an n-type tunnel layer (133) made of GaInP containing n-type impurities (Te). A highly n-type impurities-doped layer (132) having a higher concentration of n-type impurities than the n-type tunnel layer (133) is arranged between the p-type tunnel layer (131) and the n-type tunnel layer (133).

Abstract: According to one embodiment, a memory controller includes one or more processors configured to function as a writing unit and a reading unit. The writing unit writes data as threshold voltages of individual memory cells. The reading unit reads the written data by detecting threshold voltages of the individual memory cells. The reading unit includes a selecting unit, a detecting unit, and an estimating unit. The selecting unit selects a read-target memory cell. The detecting unit detects a first threshold voltage at a time of reading of the read-target memory cell, and a second threshold voltage at a time of reading of at least one of adjacent memory cells that are adjacent to the read-target memory cell. The estimating unit estimates a third threshold voltage as a threshold voltage at a time of writing in the read-target memory cell based on the first threshold voltage and the second threshold voltage.

Abstract: A data processing apparatus for compressing physical address values correlated to logical address values includes a first prediction unit that calculates a first predicted address value for a first input address value in input data to be compressed, a determination unit that selects an encoding processing for the first input address value according to the first predicted address value, and a compression unit configured to encode the first input address value according to the encoding processing selected by the determination unit.

Abstract: According to an embodiment, an image decoding apparatus includes a memory, a decoder and a first filter. The memory stores reference pixels based on pixels included in a decoded pixel block. The decoder decodes encoded data in units of pixel blocks using the reference pixels to generate a first decoded pixel block, the first decoded pixel block being adjacent to the reference pixels. The first filter performs a first filtering on only the first decoded pixel block using the first decoded pixel block and part of the reference pixels perpendicularly adjacent to the first decoded pixel block in a scan direction of image decoding processing.

Abstract: According to an embodiment, an image decoding apparatus includes a memory, a decoder and a first filter. The memory stores reference pixels based on pixels included in a decoded pixel block. The decoder decodes encoded data in units of pixel blocks using the reference pixels to generate a first decoded pixel block, the first decoded pixel block being adjacent to the reference pixels. The first filter performs a first filtering on only the first decoded pixel block using the first decoded pixel block and part of the reference pixels perpendicularly adjacent to the first decoded pixel block in a scan direction of image decoding processing.

Abstract: According to an embodiment, an image decoding apparatus includes a memory, a decoder and a first filter. The memory stores reference pixels based on pixels included in a decoded pixel block. The decoder decodes encoded data in units of pixel blocks using the reference pixels to generate a first decoded pixel block, the first decoded pixel block being adjacent to the reference pixels. The first filter performs a first filtering on only the first decoded pixel block using the first decoded pixel block and part of the reference pixels perpendicularly adjacent to the first decoded pixel block in a scan direction of image decoding processing.

Abstract: A light-emitting element layer 10 includes: an n-type contact layer 11; a first light-emitting layer 12; a tunnel junction layer 13; a second light-emitting layer 14; and a p-type contact layer 15 laminated in this order. The first light-emitting layer 12 and the second light-emitting layer 14 emit light of the same wavelength. The tunnel junction layer 13 includes: a p-type tunnel layer 131 made of AlGaAs containing p-type impurities (C); and an n-type tunnel layer 133 made of GaInP containing n-type impurities (Te). A highly n-type impurities-doped layer 132 having a higher concentration of n-type impurities than the n-type tunnel layer 133 is arranged between the p-type tunnel layer 131 and the n-type tunnel layer 133.

Abstract: According to one embodiment, a memory controller includes one or more processors configured to function as a writing unit and a reading unit. The writing unit writes data as threshold voltages of individual memory cells. The reading unit reads the written data by detecting threshold voltages of the individual memory cells. The reading unit includes a selecting unit, a detecting unit, and an estimating unit. The selecting unit selects a read-target memory cell. The detecting unit detects a first threshold voltage at a time of reading of the read-target memory cell, and a second threshold voltage at a time of reading of at least one of adjacent memory cells that are adjacent to the read-target memory cell. The estimating unit estimates a third threshold voltage as a threshold voltage at a time of writing in the read-target memory cell based on the first threshold voltage and the second threshold voltage.

Abstract: According to an embodiment, a readout control device includes a memory and one or more processors configured to function as a converter, a reader and an analyzer. The converter converts a logical address of a compressed cluster that is a readout target into a physical address in a non-volatile memory. The reader reads out, from the non-volatile memory, data included in a packing unit at a position indicated by the physical address. The analyzer analyzes header information included in the packing unit, in parallel to reading of the data included in the packing unit, and acquires position information of the compressed cluster that is the readout target in the packing unit.

Abstract: According to an embodiment, an encoding device includes a determination unit, a first palette generator, a first assignment unit, an encoder, and a first reference generator. The determination unit is configured to determine an additional palette that holds a color not included in a reference palette among colors included in a predetermined operation unit of an input image. The first palette generator is configured to generate a palette for encoding including a color included in the additional palette and a color included in the reference palette. The first assignment unit is configured to assign, to each pixel in the operation unit, an index indicating a color in the palette for encoding corresponding to a color of the pixel. The encoder is configured to encode the index and information on the additional palette. The first reference generator is configured to generate the reference palette from the palette for encoding.

Abstract: According to an embodiment, a data processing apparatus includes a divider, a hash calculator, a hash memory, an access controller, and a compressor. The divider is configured to divide input data into blocks. The hash calculator is configured to calculate hash values from the respective blocks. The hash memory is configured to store pieces of first data that are based on the respective blocks. The access controller is configured to access the hash memory by using the hash values, read one or some of the pieces of first data, each stored at an address indicated by each hash value, from the hash memory, and write, at the addresses indicated by the hash values, pieces of first data that are determined based on the respective blocks. The compressor is configured to compress the input data into compressed data based on the input data and the read pieces of first data.

Abstract: A multilayer plate, comprising a layer composed of a methacrylic resin comprising not less than 90% by mass of a structural unit derived from a methacrylic acid ester such as methyl methacrylate, methacrylic esters of a polycyclic aliphatic hydrocarbon and the like and having a glass transition temperature of 120 to 180° C., and a layer composed of a polycarbonate resin.

Abstract: A methacrylic resin composition, which comprises a methacrylic resin comprising 99.5% by mass or more of a structural unit derived from methyl methacrylate. The methacrylic resin includes less than 0.03 mol % of terminal double bonds based on the amount of the structural unit derived from methyl methacrylate and 0.2 mol % or more of combined sulfur atoms based on the amount of the structural unit derived from methyl methacrylate. The methacrylic resin composition has a melt flow rate of 8 g/10 min or more at 230° C. and a load of 3.8 kg.

Abstract: Provided are a light-emitting diode which prevents degradation of reflectance and which enables high-luminosity light emission, and its manufacturing method. Such a light-emitting diode includes a substrate (1) upon which are provided, in this order, a reflecting layer (6), a transparent film (8) wherein multiple ohmic contact electrodes (7) are embedded at intervals, and a compound semiconductor layer (10) including a current diffusion layer (25) and a light-emitting layer (24) in this order. The periphery of the surface of each ohmic contact electrode (7) on the substrate (1) side are covered by the transparent film (8), and the ohmic contact electrodes (7) contact the reflecting layer (6) and the current diffusion layer (25).

Abstract: In a light-emitting diode, a plurality of dot-shaped ohmic contact electrodes are provided between a metal reflective film and a compound semiconductor layer, an ohmic electrode and a surface electrode composed of a pad portion and a plurality of linear portions connected to the pad portion are provided in that order on the opposite side of the compound semiconductor layer from the semiconductor substrate, the surface of the ohmic electrode is covered with the linear portions, the ohmic contact electrodes and the ohmic electrode are formed in positions that do not overlap with the pad portion in plan view, and among the plurality of ohmic contact electrodes, 5% or more and 40% or less of the ohmic contact electrodes are disposed in positions that overlap with the linear portions in plan view.

Abstract: A light-emitting diode, a method of manufacturing the same, a lamp and an illumination device. A light-emitting diode (100) is provided with a compound semiconductor layer (10) including a light-emitting layer (24) provided on a substrate (1); an ohmic contact electrode (7) provided between the substrate and compound semiconductor layer; an ohmic electrode (11) provided on the side of the compound semiconductor layer opposite the substrate; a surface electrode (12) including a branch section (12b) provided so as to cover the surface of the ohmic electrode and a pad section (12a) coupled to the branch section; and a current-blocking portion (13) provided between an under-pad light-emitting layer (24a) arranged in an area of the light-emitting layer that overlaps the pad section (12a) and a light-emitting layer arranged in an area except the area that overlaps the pad section, to prevent current from being supplied to the under-pad light-emitting layer.

Abstract: A divider divides an input data into a plurality of data blocks. A hash calculator calculates a hash value of each data block. A compression dictionary memory stores a compression dictionary that stores a previous input data and includes a shared dictionary shared by different data lengths. A hash table memory stores a hash table that stores an address representing a storage location of the data block corresponding to the hash value on the compression dictionary for each data block and includes a shared table shared by different data lengths. An address acquirer acquires the address corresponding to the data block based on the hash table. A matcher determines sameness between the previous data block indicated by the address and the new input data. An encoder generates a compressed data that includes matching information and a matched portion is converted to the address.

Abstract: The present invention relates to an epitaxial wafer for a light-emitting diode wherein the peak emission wavelength is 655 nm or more, and it is possible to improve reliability. The epitaxial wafer for light-emitting diodes includes a GaAs substrate (1) and a pn-junction type light-emitting unit (2) provided on the GaAs substrate (1), wherein light-emitting unit (2) is formed as a multilayer structure in which a strained light-emitting layer and a barrier layer are alternately stacked, and the composition formula of the barrier layer is (AlXGa1-X)YIn1-YP (0.3?X?0.7, 0.51?Y?0.54).