Abstract: A communication device for transmitting data to an other communication device via a transmission channel, includes a communication characteristic acquisition section which acquires a communication characteristic of the transmission channel, and a frame length control section which controls a frame length of a communication frame storing the data based on the communication characteristic of the transmission channel.

Abstract: The nucleic acid probe of the invention is a nucleic acid probe for detecting a trace amount of target nucleic acid highly sensitively, highly accurately, and highly quickly, and is designed so that the nucleic acid probe undergoes a conformational change after hybridization to the target nucleic acid and that the nucleic acid probe, which underwent the conformational change, has a decreased binding strength of hybridization and dissociates from the target nucleic acid, where the conformational change comprises forming a self-cleaving nucleic acid enzyme intramolecularly and the self-cleaving nucleic acid enzyme has cleavage activity toward a cleavage portion within the nucleic acid probe's own molecule.

Abstract: An image processing apparatus enabling alpha blending or other image processing during bit block transfer (bitblt), wherein the selector 52 selects one of the primitive data S143, the image data S12 and the image data S147a that are used for the host-local transfer, and outputs the data to the alpha blend circuit 53. According to the control signal S55, the alpha blend circuit 53 turns on or turns off alpha blending. The selector 54 selects either the image data S139 or the image data S53 and writes the data to the DRAM 147.

Abstract: There is provided an information processing device which is capable of providing a program selected on the basis of a predetermined theme among recorded programs and programs to be received to a user. A special program is generated by selecting a predetermined program on the basis of a predetermined theme such as ‘person of the today’, ‘hot drama’, or the like among recorded programs and programs to be received to a user and the contents of the selected program is displayed on a screen as information of a recommendation program. The contents of the special program are changed according to preference of the user, a displaying time of the screen, and setting by the user. The invention can be applied to an information processing device which records a program or plays the recorded program.

Abstract: An image processing apparatus capable of performing a refresh operation without causing a drop in performance, an increase in cost, or damage to the apparatus. The apparatus further being capable of achieving a reduction in power consumption, and being provided with a memory I/F circuit able to not only refresh, for example, four DRAM modules simultaneously, but also capable of refreshing two DRAM modules at a same timing, then refreshing the remaining two DRAM modules simultaneously at a next timing, or refreshing the four DRAM modules one by one in order based on given refresh control data, and controlling the timing of the refresh operation for each divided DRAM module.

Abstract: The multi-tube heat exchanger includes a bundle of tubes which form fluid passages of first heat exchanging fluid, an outer shell which covers the bundle of tubes and form a fluid passage of second heat exchanging fluid, and a baffle plate which is arranged inside the outer shell in a direction intersecting an axial direction of the bundle of tubes and provided with a plurality of through holes through which respective tubes of the bundle are passed. Each of the through holes has such a shape that a portion of an outer peripheral face of the tube comes into contact with a portion of an inner peripheral face of the through hole, and a gap for passing the second heat exchanging fluid is formed between the other portion of the inner peripheral face and the outer peripheral face of the tube. It is possible to support the tubes with high dimensional accuracy, and to enhance heat exchanging efficiency by decreasing fluid resistance.

Abstract: An image data processing apparatus capable of performing processing at a high speed comprising a DRAM for storing display data including a plurality of first pixel data respectively indicating colors of a plurality of pixels arranged in a matrix and able to be simultaneously written with a plurality of first pixel data. Memory controllers are provided with a plurality of pixel data generation circuits provided corresponding to the plurality of first pixel data to be simultaneously written for performing color blending using the second pixel data and the third pixel data for blending a color indicated by corresponding second pixel data and a color indicated by third pixel data stored in the write address by a predetermined blending ratio to generate a new color so as to generate the first pixel data indicating the new color.

Abstract: An image processing apparatus enabling alpha blending or other image processing during bit block transfer (bitblt), wherein the selector 52 selects one of the primitive data S143, the image data S12 and the image data S147a that are used for the host-local transfer, and outputs the data to the alpha blend circuit 53. According to the control signal S55, the alpha blend circuit 53 turns on or turns off alpha blending. The selector 54 selects either the image data S139 or the image data S53 and writes the data to the DRAM 147.

Abstract: An image processing apparatus capable of performing a refresh operation without causing a drop in performance, an increase of the cost, and damage to the apparatus and achieving a reduction of the power consumption, provided with a memory I/F circuit able to not only refresh for example four DRAM modules simultaneously, but also refresh two DRAM modules at a same timing, then refresh the remaining two DRAM modules simultaneously at a next timing or refresh the four DRAM modules one by one in order based on given refresh control data and controlling the timing of the refresh operation for each divided DRAM module.

Abstract: A video signal format converting circuit is disclosed, comprising a signal converting matrix circuit and a filter circuit that is constructed of a time delaying device for a video signal corresponding to a standard television format. When a digital video signal corresponding to a first video signal format is converted into a second video signal format that is different from the first video signal format and then output, the time delaying device of the filter circuit is used as a delaying circuit. The output signal of the delaying circuit or the video signal corresponding to the standard television signal format is selectively output. While or after the video signal corresponding to the first video signal format is converted into the video signal corresponding to the second signal format, the video signal is modified so as to protect it from being copied.

Abstract: A video signal format converting circuit is disclosed, comprising a signal converting matrix circuit and a filter circuit that is constructed of a time delaying device for a video signal corresponding to a standard television format. When a digital video signal corresponding to a first video signal format is converted into a second video signal format that is different from the first video signal format and then output, the time delaying device of the filter circuit is used as a delaying circuit. The output signal of the delaying circuit or the video signal corresponding to the standard television signal format is selectively output. While or after the video signal corresponding to the first video signal format is converted into the video signal corresponding to the second signal format, the video signal is modified so as to protect it from being copied.

Abstract: A video signal format converting circuit is disclosed, comprising a signal converting matrix circuit and a filter circuit that is constructed of a time delaying device for a video signal corresponding to a standard television format. When a digital video signal corresponding to a first video signal format is converted into a second video signal format that is different from the first video signal format and then output, the time delaying device of the filter circuit is used as a delaying circuit. The output signal of the delaying circuit or the video signal corresponding to the standard television signal format is selectively output. While or after the video signal corresponding to the first video signal format is converted into the video signal corresponding to the second signal format, the video signal is modified so as to protect it from being copied.