Patents by Inventor Atsushi Nishikizawa
Atsushi Nishikizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8367479Abstract: To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened.Type: GrantFiled: March 5, 2010Date of Patent: February 5, 2013Assignee: Renesas Electronics CorporationInventors: Hiroyuki Nakamura, Akira Muto, Nobuya Koike, Atsushi Nishikizawa, Yukihiro Sato, Katsuhiko Funatsu
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Patent number: 8338927Abstract: The semiconductor device includes a semiconductor chip, a chip mounting portion, a suspension lead, and a plurality of leads. Each of the plurality of leads has a first part and a second part, and the suspension lead has a first part and a second part. The first part of each of the plurality of leads and the suspension lead project from the plurality of side surfaces of the sealing body, respectively. Parts of the side surfaces of the plurality of leads and the suspension lead are exposed from the plurality of side surfaces of the sealing body, respectively. An area of the obverse surface of the first part of the suspension lead is larger than an area of the obverse surface of the first part of each of the plurality of leads in a plan view.Type: GrantFiled: September 6, 2011Date of Patent: December 25, 2012Assignee: Renesas Electronics CorporationInventors: Hiroyuki Nakamura, Atsushi Nishikizawa, Nobuya Koike
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Patent number: 8298859Abstract: There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire.Type: GrantFiled: February 25, 2011Date of Patent: October 30, 2012Assignee: Renesas Electronics CorporationInventors: Nobuya Koike, Tsukasa Matsushita, Hiroshi Sato, Keiichi Okawa, Atsushi Nishikizawa
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Publication number: 20110316137Abstract: The semiconductor device includes a semiconductor chip, a chip mounting portion, a suspension lead, and a plurality of leads. Each of the plurality of leads has a first part and a second part, and the suspension lead has a first part and a second part. The first part of each of the plurality of leads and the suspension lead project from the plurality of side surfaces of the sealing body, respectively. Parts of the side surfaces of the plurality of leads and the suspension lead are exposed from the plurality of side surfaces of the sealing body, respectively. An area of the obverse surface of the first part of the suspension lead is larger than an area of the obverse surface of the first part of each of the plurality of leads in a plan view.Type: ApplicationFiled: September 6, 2011Publication date: December 29, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki NAKAMURA, Atsushi NISHIKIZAWA, Nobuya KOIKE
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Patent number: 8026130Abstract: A method is provided for manufacturing a QFN type semiconductor integrated circuit device using a multi-device lead frame having a tie bar for tying external end portions of plural leads, wherein sealing resin filled between an outer periphery of a mold cavity and the tie bar is removed by a laser and thereafter a surface treatment such as solder plating is performed.Type: GrantFiled: April 29, 2009Date of Patent: September 27, 2011Assignee: Renesas Electronics CorporationInventors: Hiroyuki Nakamura, Atsushi Nishikizawa, Nobuya Koike
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Patent number: 7968370Abstract: There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire 29.Type: GrantFiled: November 7, 2008Date of Patent: June 28, 2011Assignee: Renesas Electronics CorporationInventors: Nobuya Koike, Tsukasa Matsushita, Hiroshi Sato, Keiichi Okawa, Atsushi Nishikizawa
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Publication number: 20110143500Abstract: There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire 29.Type: ApplicationFiled: February 25, 2011Publication date: June 16, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Nobuya KOIKE, Tsukasa MATSUSHITA, Hiroshi SATO, Keiichi OKAWA, Atsushi NISHIKIZAWA
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Publication number: 20100258922Abstract: To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened.Type: ApplicationFiled: March 5, 2010Publication date: October 14, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hiroyuki NAKAMURA, Akira MUTO, Nobuya KOIKE, Atsushi NISHIKIZAWA, Yukihiro SATO, Katsuhiko FUNATSU
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Publication number: 20090317948Abstract: A method is provided for manufacturing a QFN type semiconductor integrated circuit device using a multi-device lead frame having a tie bar for tying external end portions of plural leads, wherein sealing resin filled between an outer periphery of a mold cavity and the tie bar is removed by a laser and thereafter a surface treatment such as solder plating is performed.Type: ApplicationFiled: April 29, 2009Publication date: December 24, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hiroyuki NAKAMURA, Atsushi NISHIKIZAWA, Nobuya KOIKE
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Publication number: 20090068796Abstract: There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire 29.Type: ApplicationFiled: November 7, 2008Publication date: March 12, 2009Inventors: Nobuya Koike, Tsukasa Matsushita, Hiroshi Sato, Keiichi Okawa, Atsushi Nishikizawa
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Patent number: 7462887Abstract: There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross-section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire 29.Type: GrantFiled: August 14, 2006Date of Patent: December 9, 2008Assignee: Renesas Technology Corp.Inventors: Nobuya Koike, Tsukasa Matsushita, Hiroshi Sato, Keiichi Okawa, Atsushi Nishikizawa
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Publication number: 20070040187Abstract: There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire 29.Type: ApplicationFiled: August 14, 2006Publication date: February 22, 2007Inventors: Nobuya Koike, Tsukasa Matsushita, Hiroshi Sato, Keiichi Okawa, Atsushi Nishikizawa
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Patent number: 6492739Abstract: A QFP adapted to lowering the heat resistance and increasing the number of pins, and a method of producing the same. The QFP includes a heat-radiating metal plate having bumpers formed at the four corners thereof as a unitary structure, a semiconductor chip mounted on the heat-radiating metal plate, leads provided on the heat-radiating metal plate and surrounding the peripheries of the semiconductor chip, bonding wires for connecting the leads to the semiconductor chip, and a sealing resin member for sealing part of the semiconductor chip, inner leads of the leads, bonding wires and part of the heat-radiating metal plate. The tips of the bumpers integrally formed with the heat-radiating metal plate are positioned outside the tips of the outer leads that are protruding from the sealing resin member. In the QFP producing method, the heat-radiating metal plate having the bumpers and the lead frame having the leads are secured outside the sealing resin member.Type: GrantFiled: March 25, 2002Date of Patent: December 10, 2002Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.Inventors: Kuniharu Muto, Atsushi Nishikizawa, Jyunichi Tsuchiya, Toshiyuki Hata, Nobuya Koike, Ichio Shimizu
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Publication number: 20020096791Abstract: A QFP adapted to lowering the heat resistance and increasing the number of pins, and a method of producing the same. The QFP includes a heat-radiating metal plate having bumpers formed at the four corners thereof as a unitary structure, a semiconductor chip mounted on the heat-radiating metal plate, leads provided on the heat-radiating metal plate and surrounding the peripheries of the semiconductor chip, bonding wires for connecting the leads to the semiconductor chip, and a sealing resin member for sealing part of the semiconductor chip, inner leads of the leads, bonding wires and part of the heat-radiating metal plate. The tips of the bumpers integrally formed with the heat-radiating metal plate are positioned outside the tips of the outer leads that are protruding from the sealing resin member. In the QFP producing method, the heat- radiating metal plate having the bumpers and the lead frame having the leads are secured outside the sealing resin member.Type: ApplicationFiled: March 25, 2002Publication date: July 25, 2002Applicant: Hitachi, Ltd.Inventors: Kuniharu Muto, Atsushi Nishikizawa, Jyunichi Tsuchiya, Toshiyuki Hata, Nobuya Koike, Ichio Shimizu
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Patent number: 6392308Abstract: A QFP adapted to lowering the heat resistance and increasing the number of pins, and a method of producing the same. The QFP includes a heat-radiating metal plate having bumpers formed at the four corners thereof as a unitary structure, a semiconductor chip mounted on the heat-radiating metal plate, leads provided on the heat-radiating metal plate and surrounding the peripheries of the semiconductor chip, bonding wires for connecting the leads to the semiconductor chip, and a sealing resin member for sealing part of the semiconductor chip, inner leads of the leads, bonding wires and part of the heat-radiating metal plate. The tips of the bumpers integrally formed with the heat-radiating metal plate are positioned outside the tips of the outer leads that are protruding from the sealing resin member. In the QFP producing method, the heat-radiating metal plate having the bumpers and the lead frame having the leads are secured outside the sealing resin member.Type: GrantFiled: February 28, 2001Date of Patent: May 21, 2002Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.Inventors: Kuniharu Muto, Atsushi Nishikizawa, Jyunichi Tsuchiya, Toshiyuki Hata, Nobuya Koike, Ichio Shimizu
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Patent number: 6320270Abstract: A QFP adapted to lowering the heat resistance and increasing the number of pins, and a method of producing the same. The QFP includes a heat-radiating metal plate having bumpers formed at the four corners thereof as a unitary structure, a semiconductor chip mounted on the heat-radiating metal plate, leads provided on the heat-radiating metal plate and surrounding the peripheries of the semiconductor chip, bonding wires for connecting the leads to the semiconductor chip, and a sealing resin member for sealing part of the semiconductor chip, inner leads of the leads, bonding wires and part of the heat-radiating metal plate. The tips of the bumpers integrally formed with the heat-radiating metal plate are positioned outside the tips of the outer leads that are protruding from the sealing resin member. In the QFP producing method, the heat- radiating metal plate having the bumpers and the lead frame having the leads are secured outside the sealing resin member.Type: GrantFiled: February 9, 2000Date of Patent: November 20, 2001Assignee: Hitachi, Ltd.Inventors: Kuniharu Muto, Atsushi Nishikizawa, Jyunichi Tsuchiya, Toshiyuki Hata, Nobuya Koike, Ichio Shimizu
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Publication number: 20010006259Abstract: A QFP adapted to lowering the heat resistance and increasing the number of pins, and a method of producing the same. The QFP includes a heat-radiating metal plate having bumpers formed at the four corners thereof as a unitary structure, a semiconductor chip mounted on the heat-radiating metal plate, leads provided on the heat-radiating metal plate and surrounding the peripheries of the semiconductor chip, bonding wires for connecting the leads to the semiconductor chip, and a sealing resin member for sealing part of the semiconductor chip, inner leads of the leads, bonding wires and part of the heat-radiating metal plate. The tips of the bumpers integrally formed with the heat-radiating metal plate are positioned outside the tips of the outer leads that are protruding from the sealing resin member. In the QFP producing method, the heat- radiating metal plate having the bumpers and the lead frame having the leads are secured outside the sealing resin member.Type: ApplicationFiled: February 28, 2001Publication date: July 5, 2001Applicant: Hitachi, Ltd.Inventors: Kuniharu Muto, Atsushi Nishikizawa, Jyunichi Tsuchiya, Toshiyuki Hata, Nobuya Koike, Ichio Shimizu
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Patent number: 6104085Abstract: A QFP adapted to lowering the heat resistance and increasing the number of pins, and a method of producing the same. The QFP includes a heat-radiating metal plate having bumpers formed at the four corners thereof as a unitary structure, a semiconductor chip mounted on the heat-radiating metal plate, leads provided on the heat-radiating metal plate and surrounding the peripheries of the semiconductor chip, bonding wires for connecting the leads to the semiconductor chip, and a sealing resin member for sealing part of the semiconductor chip, inner leads of the leads, bonding wires and part of the heat-radiating metal plate. The tips of the bumpers integrally formed with the heat-radiating metal plate are positioned outside the tips of the outer leads that are protruding from the sealing resin member. In the QFP producing method, the heat-radiating metal plate having the bumpers and the lead frame having the leads are secured outside the sealing resin member.Type: GrantFiled: April 27, 1999Date of Patent: August 15, 2000Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.Inventors: Kuniharu Muto, Atsushi Nishikizawa, Jyunichi Tsuchiya, Toshiyuki Hata, Nobuya Koike, Ichio Shimizu
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Patent number: 5808359Abstract: A QFP adapted to lowering the heat resistance and increasing the number of pins includes a heat-radiating metal plate having bumpers formed at the four corners thereof as a unitary structure, a semiconductor chip mounted on the heat-radiating metal plate, leads provided on the heat-radiating metal plate and surrounding the peripheries of the semiconductor chip, bonding wires for connecting the leads to the semiconductor chip, and a sealing resin member for sealing part of the semiconductor chip, inner leads of the leads, bonding wires and part of the heat-radiating metal plate. The tips of the bumpers integrally formed with the heat-radiating metal plate are positioned outside the tips of the outer leads that are protruding from the sealing resin member. In the QFP producing method, the heat-radiating metal plate having the bumpers and the lead frame having the leads are secured outside the sealing resin member.Type: GrantFiled: October 25, 1995Date of Patent: September 15, 1998Assignees: Hitachi, Ltd, Hitachi Tohbu Semiconductor, Ltd.Inventors: Kuniharu Muto, Atsushi Nishikizawa, Jyunichi Tsuchiya, Toshiyuki Hata, Nobuya Koike, Ichio Shimizu