Patents by Inventor Atsushi Ogura
Atsushi Ogura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111320Abstract: Provided is a voltage regulator capable of suppressing a current consumption in a non-regulation state with a simple circuit configuration. The voltage regulator includes an output transistor supplying an output voltage based on a control voltage, an error amplifier circuit supplying an amplified signal obtained by amplifying a difference between a voltage based on the output voltage and a reference voltage, a common source amplifier circuit supplying the control voltage to the output transistor based on the amplified signal, and a non-regulation state detection circuit supplying a detection signal to the common source amplifier circuit. The common source amplifier circuit includes a current control circuit including a plurality of parallel paths connecting between a control terminal of the output transistor and a power supply terminal, the plurality of parallel paths including a path to be closed in the non-regulation state and a path to be opened in the non-regulation state.Type: ApplicationFiled: September 11, 2023Publication date: April 4, 2024Inventors: Atsushi HARUYAMA, Yasuhiko OGURA, Teruo SUZUKI
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Patent number: 11827551Abstract: To provide a new technique for efficiently recovering microplastics from water to be treated, in which problems of conventional techniques such as large energy consumption are solved. A method for recovering microplastics from water to be treated containing the microplastics, the method comprising a step of allowing algae having microplastic adsorption and recovery ability to be present in the water to be treated, in which the algae are algae that secrete a sticky substance, and an amount of a sticky substance secreted by the algae is such that a volume of a sticky substance secreted to an outside of cells is 0.25 times or more and 100 times or less compared to a cell volume.Type: GrantFiled: October 26, 2022Date of Patent: November 28, 2023Assignee: Novelgen Co., Ltd.Inventors: Atsushi Ogura, Yoshihiro Kawada, Yui Sawada, Hiromasa Tabata
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Publication number: 20230357054Abstract: Provided is a technique capable of efficiently removing nitrogen contained in water to be treated and efficiently recovering microplastics from the water to be treated. An aspect of the present invention is a water treatment system 10 including an aquaculture tank 20 and a water treatment tank 30. Aquatic organisms are cultivated in the aquaculture tank 20. In the water treatment tank 30, algae having a microplastic adsorption and recovery ability grow in the water to be treated introduced from the aquaculture tank 20. The microplastics contained in the water to be treated are recovered, and the nitrogen compounds contained in the water to be treated are removed, by the algae.Type: ApplicationFiled: September 30, 2021Publication date: November 9, 2023Inventors: Atsushi OGURA, Yoshihiro KAWADA, Yui SAWADA, Hiromasa TABATA
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Publication number: 20230192519Abstract: To provide a new technique for efficiently recovering microplastics from water to be treated, in which problems of conventional techniques such as large energy consumption are solved. A method for recovering microplastics from water to be treated containing the microplastics, the method comprising a step of allowing algae having microplastic adsorption and recovery ability to be present in the water to be treated, in which the algae are algae that secrete a sticky substance, and an amount of a sticky substance secreted by the algae is such that a volume of a sticky substance secreted to an outside of cells is 0.25 times or more and 100 times or less compared to a cell volume.Type: ApplicationFiled: October 26, 2022Publication date: June 22, 2023Inventors: Atsushi OGURA, Yoshihiro KAWADA, Yui SAWADA, Hiromasa TABATA
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Patent number: 7701018Abstract: A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.Type: GrantFiled: March 22, 2005Date of Patent: April 20, 2010Assignee: NEC CorporationInventors: Shigeharu Yamagami, Hitoshi Wakabayashi, Kiyoshi Takeuchi, Atsushi Ogura, Masayasu Tanaka, Masahiro Nomura, Koichi Takeda, Toru Tatsumi, Koji Watanabe, Koichi Terashima
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Patent number: 7612416Abstract: A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion; an interlayer insulating film provided on a substrate including the transistor; and a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor, wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.Type: GrantFiled: September 29, 2004Date of Patent: November 3, 2009Assignee: NEC CorporationInventors: Kiyoshi Takeuchi, Koichi Terashima, Hitoshi Wakabayashi, Shigeharu Yamagami, Atsushi Ogura, Masayasu Tanaka, Masahiro Nomura, Koichi Takeda, Toru Tatsumi, Koji Watanabe
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Patent number: 7605443Abstract: The present invention relates to a method of manufacturing a semiconductor substrate, which enables a semiconductor device to have high speed operating characteristics and high performance characteristics such as lower electrical power consumption, and a method of manufacturing a semiconductor device including a method of manufacturing the semiconductor substrate thereof in a process, as well as to a semiconductor substrate manufactured by the method of manufacturing the same and a semiconductor device manufactured using the semiconductor substrate.Type: GrantFiled: May 8, 2003Date of Patent: October 20, 2009Assignee: NEC CorporationInventor: Atsushi Ogura
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Publication number: 20080251849Abstract: A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.Type: ApplicationFiled: March 22, 2005Publication date: October 16, 2008Inventors: Shigeharu Yamagami, Hitoshi Wakabayashi, Kiyoshi Takeuchi, Atsushi Ogura, Masayasu Tanaka, Masahiro Nomura, Koichi Takeda, Toru Tatsumi, Koji Watanabe, Koichi Terashima
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Patent number: 7312140Abstract: A technique is provided that is capable of employing raw materials having no halogen, which has a high possibility of exerting a bad influence upon semiconductor elements, thereby to easily form molybdenum films (molybdenum silicide films or molybdenum nitride films) of which purity is high at a low temperature. A film forming material for forming molybdenum films, molybdenum silicide films, or tungasten nitride films is provided, wherein a Mo source of said film is one or more chemical compounds selected from the group consisting of a hexadimethylaminodimolybdenum, a hexaethylmethylaminodimolybdenum, and a hexadiethylaminodimolybdenum.Type: GrantFiled: June 1, 2005Date of Patent: December 25, 2007Assignee: Tri Chemical Laboratories Inc.Inventors: Hideaki Machida, Yoshio Ohshita, Atsushi Ogura, Masato Ishikawa
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Publication number: 20070187682Abstract: There is provided a semiconductor device comprising an n-type and a p-type field effect transistors, meeting the conditions that in terms of a crystal orientation of the protruding semiconductor region constituting the n-type field effect transistor, its plane parallel to the substrate is substantially a {100} plane and its side surface is a {100} plane substantially orthogonal to the {100} plane, and that in terms of a crystal orientation of the protruding semiconductor region constituting the p-type field effect transistor, its plane parallel to the substrate is substantially a {100} plane and its side surface is a {110} plane substantially orthogonal to the {100} plane.Type: ApplicationFiled: August 27, 2004Publication date: August 16, 2007Inventors: Kiyoshi Takeuchi, Koji Watanabe, Koichi Terashima, Atsushi Ogura, Toru Tatsumi, Koichi Takeda, Masahiro Nomura, Masayasu Tanaka, Shigeharu Yamagami, Hitoshi Wakabayashi
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Publication number: 20070132009Abstract: A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion; an interlayer insulating film provided on a substrate including the transistor; and a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor, wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.Type: ApplicationFiled: September 29, 2004Publication date: June 14, 2007Inventors: Kiyoshi Takeuchi, Koichi Terashima, Hitoshi Wakabayashi, Shigeharu Yamagami, Atsushi Ogura, Masayasu Tanaka, Masahiro Nomura, Koichi Takeda, Toru Tatsumi, Koji Watanabe
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Publication number: 20070075372Abstract: There is provided a semiconductor device wherein at least the largest width of a source/drain region is larger than the width of a semiconductor region and the source/drain region has a slope having a width continuously increasing from the uppermost side to the substrate side, and a silicide film is formed in the surface of the slope.Type: ApplicationFiled: October 19, 2004Publication date: April 5, 2007Inventors: Koichi Terashima, Kiyoshi Takeuchi, shigeharu Yamagami, Hitoshi Wakabayashi, Atsushi Ogura, Koji Watanabe, Toru Tatsumi, Koichi Takeda, Masahiro Nomura, Masayasu Tanaka
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Publication number: 20060068103Abstract: A technique is provided that is capable of employing raw materials having no halogen, which has a high possibility of exerting a bad influence upon semiconductor elements, thereby to easily form tungsten films (tungsten silicide films or tungsten nitride films) of which purity is high at a low temperature. A film forming material for forming tungsten films, tungsten silicide films, or tungasten nitride films is provided, wherein a W source of said film is one or more chemical compounds selected from the group consisting of a biscyclopentadienyltungsten dihydride, a bismethylcyclopentadienyltungsten dihydride, a bisethylcyclopentadienyltungsten dihydride, and a bisisopropylcyclopentadienyltungsten dihydride.Type: ApplicationFiled: August 31, 2005Publication date: March 30, 2006Applicant: Tri Chemical Laboratories Inc.Inventors: Hideaki Machida, Yoshio Ohshita, Atsushi Ogura, Masato Ishikawa
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Publication number: 20060068100Abstract: A technique is provided that is capable of employing raw materials having no halogen, which has a high possibility of exerting a bad influence upon semiconductor elements, thereby to easily form molybdenum films (molybdenum silicide films or molybdenum nitride films) of which purity is high at a low temperature. A film forming material for forming molybdenum films, molybdenum silicide films, or tungsten nitride films is provided, wherein a Mo source of said film is one or more chemical compounds selected from the group consisting of a biscyclopentadienylmolybdenum dihydride, a bismethylcyclopentadienylmolybdenum dihydride, a bisethylcyclopentadienylmolybdenum dihydride, and a bisisopropylcyclopentadienylmolybdenum dihydride.Type: ApplicationFiled: June 1, 2005Publication date: March 30, 2006Applicant: Tri Chemical Laboratories Inc.Inventors: Hideaki Machida, Yoshio Ohshita, Atsushi Ogura, Masato Ishikawa
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Publication number: 20060067230Abstract: A technique is provided that is capable of employing raw materials having no halogen, which has a high possibility of exerting a bad influence upon semiconductor elements, thereby to easily form molybdenum films (molybdenum silicide films or molybdenum nitride films) of which purity is high at a low temperature. A film forming material for forming molybdenum films, molybdenum silicide films, or tungasten nitride films is provided, wherein a Mo source of said film is one or more chemical compounds selected from the group consisting of a hexadimethylaminodimolybdenum, a hexaethylmethylaminodimolybdenum, and a hexadiethylaminodimolybdenum.Type: ApplicationFiled: June 1, 2005Publication date: March 30, 2006Applicant: Tri Chemical Laboratories Inc.Inventors: Hideaki Machida, Yoshio Ohshita, Atsushi Ogura, Masato Ishikawa
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Publication number: 20060068101Abstract: A technique is provided that is capable of employing raw materials having no halogen, which has a high possibility of exerting a bad influence upon semiconductor elements, thereby to easily form tungsten films (tungsten silicide films or tungsten nitride films) of which purity is high at a low temperature. A film forming material for forming tungsten films, tungsten silicide films, or tungasten nitride films is provided, wherein a W source of said film is one or more chemical compounds selected from the group consisting of a hexadimethylaminoditungsten, a hexaethylmethylaminoditungsten, and a hexadiethylaminoditungsten.Type: ApplicationFiled: June 1, 2005Publication date: March 30, 2006Applicant: Tri Chemical Laboratories Inc.Inventors: Hideaki Machida, Yoshio Ohshita, Atsushi Ogura, Masato Ishikawa
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Publication number: 20060030161Abstract: A technique capable of forming an NiSi film having excellent characteristics, which TiSi2 or CoSi2 produced thus far is not able to assume, without damaging a substrate is provided. A film forming material for forming a nickel silicide film or a Nickel film is provided, wherein an Ni source of said film is Ni(PF3)4.Type: ApplicationFiled: April 29, 2005Publication date: February 9, 2006Applicant: Tri Chemical Laboratories Inc.Inventors: Hideaki Machida, Yoshio Ohshita, Atsushi Ogura, Masato Ishikawa, Takeshi Kada
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Patent number: 6933569Abstract: A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.Type: GrantFiled: September 24, 2003Date of Patent: August 23, 2005Assignee: NEC CorporationInventors: Risho Koh, Shigeharu Yamagami, Jong-wook Lee, Hitoshi Wakabayashi, Yukishige Saito, Atsushi Ogura, Mitsuru Narihiro, Kohichi Arai, Hisashi Takemura, Tohru Mogami, Toyoji Yamamoto, Yukinori Ochiai
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Publication number: 20050176222Abstract: The present invention relates to a method of manufacturing a semiconductor substrate, which enables a semiconductor device to have high speed operating characteristics and high performance characteristics such as lower electrical power consumption, and a method of manufacturing a semiconductor device including a method of manufacturing the semiconductor substrate thereof in a process, as well as to a semiconductor substrate manufactured by the method of manufacturing the same and a semiconductor device manufactured using the semiconductor substrate.Type: ApplicationFiled: May 8, 2003Publication date: August 11, 2005Inventor: Atsushi Ogura
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Patent number: 6919563Abstract: Disclosed is a defect evaluation apparatus comprising a source section having a source for generating positrons and a moderator for decelerating the positrons, a sample holding section for holding a sample to be measured, a transfer section for transferring the positrons from the source section to the sample holding section, and detection means for detecting ? rays emitted from the sample being measured, characterized in that the apparatus further comprises heating means for heating the moderator in a position where there is a possibility of the source being thermally damaged if there is no protection means mentioned below in the source section, and protection means for protecting the source from the heating means and heated moderator when the moderator is being heated using the heating means.Type: GrantFiled: August 28, 2003Date of Patent: July 19, 2005Assignee: Semiconductor Technology Academic Research CenterInventors: Akira Uedono, Atsushi Ogura