Patents by Inventor Atsushi Sasaki

Atsushi Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9045240
    Abstract: A flight control method and device for correcting a reference trajectory based on a distance from a current position to a target position in a spacecraft in flight. A CPU included in the spacecraft generates a reference trajectory which is a trajectory for allowing the spacecraft in flight to arrive at the target position on a celestial body with the atmosphere, and which is identified based on velocity or energy of the spacecraft and on drag acceleration of the spacecraft. The CPU calculates a ratio between the range that is a distance from the current position based on the reference trajectory to the target position, and the real range that is a real distance from a current position to the target position, and corrects the reference trajectory by calculating the drag acceleration in the reference trajectory using the calculated ratio.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: June 2, 2015
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Tetsuya Nagase, Atsushi Sasaki
  • Patent number: 8987041
    Abstract: Certain embodiments provide method for manufacturing a solid-state imaging device, including forming an electrode and forming a second impurity layer. The electrode is formed on a semiconductor substrate including a first impurity layer of a first conductivity type on a surface. The second impurity layer is a second conductivity type and is formed by implanting an impurity of a second conductivity type into the first impurity layer in an oblique direction with respect to the surface of the semiconductor substrate on the condition that the impurity penetrates an end portion of the electrode, based on a position of the electrode. The second impurity layer is bonded to the first impurity layer to constitute a photodiode, and a portion of the second impurity layer is disposed under the electrode.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ken Tomita, Atsushi Sasaki
  • Publication number: 20150076467
    Abstract: A method of manufacturing a thin film transistor (TFT) substrate in which a TFT including an oxide semiconductor layer is formed, the method including: forming an insulating layer to cover the oxide semiconductor layer; and forming an opening in the insulating layer, wherein the insulating layer includes a first film, a second film which is provided above the first film and is an aluminum oxide film, and a third film which is provided above the second film and is a film including silicon, and the forming of an opening includes: forming a resist pattern above the third film; processing the third film by dry etching; and processing the second film by wet etching.
    Type: Application
    Filed: June 19, 2013
    Publication date: March 19, 2015
    Applicant: PANASONIC CORPORATION
    Inventors: Atsushi Sasaki, Eiichi Satoh, Hirofumi Higashi
  • Publication number: 20150055033
    Abstract: The purpose of the present invention is to provide a transparent electroconductive laminate having extremely high visibility.
    Type: Application
    Filed: March 19, 2013
    Publication date: February 26, 2015
    Applicant: Teijin Limited,
    Inventors: Koichi Imamura, Ryuhei Kanzaki, Atsushi Sasaki, Yohei Okada, Kazuhito Kobayashi, Yusuke Nakata
  • Patent number: 8908246
    Abstract: An image reading device has a light source and an image sensor configured to transfer an electric charge accumulated on an opto-electric conversion element to a shift register through a shift gate. A reading controller configured to control image reading inserts a dummy interval into a shift period for which the electric charge is transferred from the opto-electric conversion element so as to shift timing to start sensor reading on every line and to arrange peak positions of noise included in a read image differ from one another on every line.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: December 9, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Atsushi Sasaki
  • Patent number: 8846180
    Abstract: A retardation film which has few foreign matter defects and small retardation nonuniformity and meets the required quality of a retardation film is provided with high productivity at a low cost by melt extruding a polycarbonate. The retardation film obtained by stretching and orienting a melt extruded film of a polycarbonate is characterized in that: (1) the polycarbonate constituting the film has a viscosity average molecular weight of 1.3×104 to 1.8×104; (2) the retardation R(589) within the plane of the film measured at a wavelength of 589 nm is 50 to 800 nm; (3) the retardation R(589) nonuniformity within the plane of the film is ±5 nm; (4) the average thickness of the film is 10 to 150 ?m; and (5) the number of film defects as large as 100 ?m or more is 2 or less/m2.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: September 30, 2014
    Assignee: Teijin Chemicals, Ltd.
    Inventors: Hideaki Nitta, Junichi Shibata, Atsushi Sasaki, Masahiro Murakami
  • Publication number: 20140191231
    Abstract: According to one embodiment, a method of manufacturing a thin-film transistor circuit substrate including forming an oxide semiconductor thin film above an insulative substrate, forming a gate insulation film and a gate electrode which are stacked on a first region of the oxide semiconductor thin film, and exposing from the gate insulation film a second region and a third region of the oxide semiconductor thin film, the second region and the third region being located on both sides of the first region of the oxide semiconductor thin film, forming an interlayer insulation film of silicon nitride including dangling bonds of silicon, the interlayer insulation film covering the second region and the third region of the oxide semiconductor thin film, the gate insulation film and the gate electrode, and forming a source electrode and a drain electrode.
    Type: Application
    Filed: March 12, 2014
    Publication date: July 10, 2014
    Applicant: JAPAN DISPLAY INC.
    Inventors: Tetsuya SHIBATA, Hajime Watakabe, Atsushi Sasaki, Yuki Matsuura, Muneharu Akiyoshi, Hiroyuki Watanabe
  • Publication number: 20140136029
    Abstract: A flight control method and device for correcting a reference trajectory based on a distance from a current position to a target position in a spacecraft in flight. A CPU included in the spacecraft generates a reference trajectory which is a trajectory for allowing the spacecraft in flight to arrive at the target position on a celestial body with the atmosphere, and which is identified based on velocity or energy of the spacecraft and on drag acceleration of the spacecraft. The CPU calculates a ratio between the range that is a distance from the current position based on the reference trajectory to the target position, and the real range that is a real distance from a current position to the target position, and corrects the reference trajectory by calculating the drag acceleration in the reference trajectory using the calculated ratio.
    Type: Application
    Filed: July 11, 2012
    Publication date: May 15, 2014
    Inventors: Tetsuya Nagase, Atsushi Sasaki
  • Patent number: 8710498
    Abstract: According to one embodiment, a method of manufacturing a thin-film transistor circuit substrate including forming an oxide semiconductor thin film above an insulative substrate, forming a gate insulation film and a gate electrode which are stacked on a first region of the oxide semiconductor thin film, and exposing from the gate insulation film a second region and a third region of the oxide semiconductor thin film, the second region and the third region being located on both sides of the first region of the oxide semiconductor thin film, forming an interlayer insulation film of silicon nitride including dangling bonds of silicon, the interlayer insulation film covering the second region and the third region of the oxide semiconductor thin film, the gate insulation film and the gate electrode, and forming a source electrode and a drain electrode.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: April 29, 2014
    Assignee: Japan Display Inc.
    Inventors: Tetsuya Shibata, Hajime Watakabe, Atsushi Sasaki, Yuki Matsuura, Muneharu Akiyoshi, Hiroyuki Watanabe
  • Patent number: 8670940
    Abstract: A plant information management system comprising: a seed identification information input device; an individual plant identification information retrieval device; an individual plant identification information input device; a new seed identification information retrieval device; a storage location information retrieval device; a project database management device; a seed database management device; a project database memory device; and a seed database memory device.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: March 11, 2014
    Assignee: Honda Motor Co., Ltd.
    Inventors: Yoshitsugu Hirose, Shaoyang Lin, Atsushi Sasaki
  • Patent number: 8643918
    Abstract: An image reading device, which has an image sensor having a plurality of sensor chips therein and being capable of outputting data in parallel through a plurality of output channels, includes an image reading section configured to perform reading of images in either of two outputting modes, one being a parallel outputting mode in which start signals are simultaneously inputted to the plurality of sensor chips so that pieces of data in the plurality of the sensor chips are outputted in parallel through the plurality of output channels, respectively, the other one being an interval outputting mode in which start signals are sequentially inputted to the plurality of sensor chips at intervals of time between any two successive inputs of the start signals, respectively, so that respective pieces of data in the plurality of sensor chips are sequentially outputted through any one of the plurality of output channels, and a mode selection section configured to select either of the two outputting modes in accordance wi
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: February 4, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Atsushi Sasaki
  • Publication number: 20130103405
    Abstract: An operation determination processing section of a center extracts words included in the utterance of a driver and an operator, reads an attribute associated with each word from a synonym and related word in which an attribute is stored so as to be associated with each word, reads a domain of a candidate or the like for the task associated with the attribute from the synonym and related word in which domains of a candidate for a task associated with the read attribute or domains of a task to be actually performed are stored, totals the domains read for each word for words included in the utterance of the driver or the like, and estimates those related to a domain with a highest total score as the candidate for the task and the task to be actually performed. In this manner, it is possible to estimate the task with high accuracy.
    Type: Application
    Filed: April 12, 2011
    Publication date: April 25, 2013
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Toshiyuki Namba, Hiroaki Sekiyama, Tatsuyuki Oka, Minako Fujishiro, Katsutoshi Okawa, Emi Otani, Atsushi Sasaki, Yasuhiko Fujita
  • Patent number: 8399520
    Abstract: The present invention provides a compound represented by the following formula (I); [wherein T represents a single bond, a C1-C4 alkylene group which may have a substituent and the like; formula (I-1) represents a single bond or a double bond; A represents a single bond, a bivalent 5- to 14-membered heterocyclic group which may have a substituent and the like; Y represents a single bond and the like; Z represents a methylene group and the like; ring G represents a phenylene group and the like which may condense with a 5- to 6-membered ring and may have a heteroatom; Ra and Rb are the same as or different from each other and represent a hydrogen atom and the like; W represents a single bond and the like; R? represents 1 to 4 independent hydrogen atoms and the like; and R? represents 1 to 4 independent hydrogen atoms and the like] or a salt thereof, or a hydrate thereof.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: March 19, 2013
    Assignee: Eisai R&D Management Co., Ltd.
    Inventors: Shinichi Hamaoka, Noritaka Kitazawa, Kazumasa Nara, Atsushi Sasaki, Atsushi Kamada, Tadashi Okabe
  • Publication number: 20120329201
    Abstract: Certain embodiments provide method for manufacturing a solid-state imaging device, including forming an electrode and forming a second impurity layer. The electrode is formed on a semiconductor substrate including a first impurity layer of a first conductivity type on a surface. The second impurity layer is a second conductivity type and is formed by implanting an impurity of a second conductivity type into the first impurity layer in an oblique direction with respect to the surface of the semiconductor substrate on the condition that the impurity penetrates an end portion of the electrode, based on a position of the electrode. The second impurity layer is bonded to the first impurity layer to constitute a photodiode, and a portion of the second impurity layer is disposed under the electrode.
    Type: Application
    Filed: March 12, 2012
    Publication date: December 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ken TOMITA, Atsushi SASAKI
  • Patent number: 8295429
    Abstract: A CCD color image sensor which prevents unnecessary charge from overflowing in a photoelectric conversion element. An image input apparatus having the CCD color image sensor comprises transferring unit which transfers effective charge accumulated in the photoelectric conversion element provided for each of the colors (R, G and B), extracted as an output signal, to a shift register by opening a shift gate; and discarding unit which discards unnecessary charge accumulated in the photoelectric conversion element by opening the shift gate at different timing from one color to another immediately before the photoelectric conversion element starts accumulating effective charge again. The discarding unit discards unnecessary charge immediately before effective charge accumulates, and discards unnecessary charge by opening the shift gate before unnecessary charge overflows in the photoelectric conversion element.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: October 23, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Atsushi Sasaki
  • Publication number: 20120199827
    Abstract: According to one embodiment, a method of manufacturing a thin-film transistor circuit substrate including forming an oxide semiconductor thin film above an insulative substrate, forming a gate insulation film and a gate electrode which are stacked on a first region of the oxide semiconductor thin film, and exposing from the gate insulation film a second region and a third region of the oxide semiconductor thin film, the second region and the third region being located on both sides of the first region of the oxide semiconductor thin film, forming an interlayer insulation film of silicon nitride including dangling bonds of silicon, the interlayer insulation film covering the second region and the third region of the oxide semiconductor thin film, the gate insulation film and the gate electrode, and forming a source electrode and a drain electrode.
    Type: Application
    Filed: December 19, 2011
    Publication date: August 9, 2012
    Inventors: Tetsuya Shibata, Hajime Watakabe, Atsushi Sasaki, Yuki Matsuura, Muneharu Akiyoshi, Hiroyuki Watanabe
  • Patent number: 8136479
    Abstract: A plasma treatment apparatus generates a plasma in a treatment vessel by an electromagnetic wave radiated from an electromagnetic wave radiation portion into the treatment vessel to perform plasma treatment by the plasma. At least a part of a wall constituting the treatment vessel includes at least a part of an electromagnetic wave transmission path which transmits the electromagnetic wave.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: March 20, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hideo Sugai, Tetsuya Ide, Atsushi Sasaki, Kazufumi Azuma, Yukihiko Nakata
  • Patent number: D672801
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: December 18, 2012
    Assignee: Panasonic Corporation
    Inventors: Makoto Nakamura, Atsushi Sasaki
  • Patent number: D698840
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: February 4, 2014
    Assignee: Panasonic Corporation
    Inventors: Makoto Nakamura, Atsushi Sasaki
  • Patent number: D700924
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: March 11, 2014
    Assignee: Panasonic Corporation
    Inventor: Atsushi Sasaki