Patents by Inventor Atsushi Shiraishi
Atsushi Shiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20120142806Abstract: Provided is a photosensitive composition which can be cured with low energy consumption, even when a substance (such as a colorant) that attenuates or shades an illumination light is contained in a high concentration or even when the photosensitive composition is in the form of a thick film. Specifically provided is a photosensitive composition which comprises the following four components: (1) a radical initiator (A); (2) an acid generator (B) or a base generator (C); (3) a polymerizable substance (D); and (4) a colorant (E), a metal oxide powder (F), or a metal powder (G).Type: ApplicationFiled: June 1, 2010Publication date: June 7, 2012Applicant: SANYO CHEMICAL INDUSTRIES, LTD.Inventors: Shihei Motofuji, Shintaro Higuchi, Atsushi Shiraishi, Takao Mukai, Megumu Sakakibara
-
Publication number: 20110302699Abstract: To provide a functional area partially within the toe area on the sole side of the sock. Providing a needle-lowering area 1a which is knit by needle-lowering knitting and a needle-raising area 2 which is knit by needle-raising knitting at a specified position within the toe area 4 on the sole side of sock S, these being aligned in the course direction, and providing a first functional area 1 in which the needle-lowering area 1a and/or the needle-raising area 2 is knit with a functional yarn which differs from the yarn used in knitting the other areas 11 within the toe area 4 on the sole side. A first functional member 1 can be provided within a specified portion of the toe area 4 on the sole side. If the first functional member 1 is knit with a functional yarn having high frictional resistance, it becomes possible to increase the gripping force only of that specified portion.Type: ApplicationFiled: June 10, 2011Publication date: December 15, 2011Inventors: Masatoshi Kaneda, Akinobu Iwaki, Atsushi Shiraishi
-
Patent number: 8051331Abstract: In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.Type: GrantFiled: March 26, 2009Date of Patent: November 1, 2011Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Hidefumi Oodate, Atsushi Shiraishi, Shigeo Kurakata, Kunihiro Katayama, Motoki Kanamori
-
Patent number: 8032783Abstract: The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.Type: GrantFiled: September 10, 2008Date of Patent: October 4, 2011Assignee: Renesas Electronics CorporationInventors: Shinsuke Asari, Chiaki Shinagawa, Yasuhiro Nakamura, Motoki Kanamori, Atsushi Shiraishi
-
Publication number: 20110115126Abstract: A laminated rotor core (36) wherein permanent magnets (47) are inserted in respective magnet insertion holes (46) is disposed between and pressed by an upper die (37) and a lower die (29). The upper die (37) has resin reservoir pots (50) provided above the laminated rotor core (36) and at positions corresponding to the respective magnet insertion holes (46). Raw resin material put in the resin reservoir pots (50) is heated by the upper die (37). Subsequently, the resin material in a liquefied state is ejected from the resin reservoir pots (50) by plungers (52) that are inserted and moves vertically in the resin reservoir pots (50) and is directly filled in the magnet insertion holes (46). Consequently, the respective magnet insertion holes (46) are filled with the resin material more evenly and highly reliable products can be supplied at low cost.Type: ApplicationFiled: January 24, 2011Publication date: May 19, 2011Applicant: MITSUI HIGH-TEC, INC.Inventors: Satoshi Matsubayashi, Hirotoshi Mabu, Katsumi Amano, Atsushi Shiraishi
-
Publication number: 20110058193Abstract: Disclosed is a printing apparatus including an image input unit, a first image narrowing unit, and gives a high weight for image data photographed during a time period in which the number of shots is large, a second image narrowing unit, and gives a high weight for image data photographed during a time period in which the number of shots is large, a weight synthesis unit, a layout decision unit, an image data extraction unit, an image assignment unit, an image color determination unit, and an additional information adjustment unit. The first image narrowing unit counts a group of a plurality of image data photographed at a predetermined time under a specific setting as one group including a number of shots, and calculates the number of shots for each predetermined time period based on the shooting date and time of the image data.Type: ApplicationFiled: September 7, 2010Publication date: March 10, 2011Applicant: SEIKO EPSON CORPORATIONInventor: Atsushi Shiraishi
-
Patent number: 7897089Abstract: A laminated rotor core (36) wherein permanent magnets (47) are inserted in respective magnet insertion holes (46) is disposed between and pressed by an upper die (37) and a lower die (29). The upper die (37) has resin reservoir pots (50) provided above the laminated rotor core (36) and at positions corresponding to the respective magnet insertion holes (46). Raw resin material put in the resin reservoir pots (50) is heated by the upper die (37). Subsequently, the resin material in a liquefied state is ejected from the resin reservoir pots (50) by plungers (52) that are inserted and moves vertically in the resin reservoir pots (50) and is directly filled in the magnet insertion holes (46). Consequently, the respective magnet insertion holes (46) are filled with the resin material more evenly and highly reliable products can be supplied at low cost.Type: GrantFiled: January 16, 2006Date of Patent: March 1, 2011Assignee: Mitsui High-Tec, Inc.Inventors: Satoshi Matsubayashi, Hirotoshi Mabu, Katsumi Amano, Atsushi Shiraishi
-
Publication number: 20110028585Abstract: The object of the present invention is to provide a photobase generator capable of efficiently generating amines (tertiary amines and amidine) high in catalytic activity by sensing light with a wavelength of from 350 to 500 nm (especially, from 400 to 500 nm). The present invention is a photobase generator characterized in being represented by general formula (1) or (2). Y+ is a quaternary ammonio group of general formula (3) to (5), and X? is a counter anion selected from among a borate anion, a phenolate anion, and a carboxylate anion.Type: ApplicationFiled: March 18, 2009Publication date: February 3, 2011Applicant: SAN-APRO LIMITEDInventors: Atsushi Shiraishi, Hideki Kimura
-
Publication number: 20100265282Abstract: A liquid crystal light modulator 11 modulates a light according to an effective value of a supplied drive signal. A driving apparatus 21 changes the effective value of each frame of the drive signal supplied to the liquid crystal light modulator 11 according to modulation data. The driving apparatus 21 generates the drive signal containing plural pulses in each frame. The driving apparatus 21 supplies the generated drive signal to the liquid crystal light modulator 11, thereby enabling a high-frequency drive of the liquid crystal light modulator 11.Type: ApplicationFiled: April 16, 2010Publication date: October 21, 2010Applicant: CITIZEN HOLDINGS CO., LTD.Inventors: Masafumi Ide, Atsushi Shiraishi
-
Publication number: 20100026947Abstract: The present invention is directed to the provision of a liquid crystal panel that can solve the problem that bubbles are formed in a liquid crystal layer. More specifically, the invention provides a liquid crystal panel includes a first plastic substrate; a second plastic substrate, a liquid crystal layer sealed between the first and second plastic substrates, a transparent conductive layer provided on the first or the second plastic substrate and having a patterned region for driving the liquid crystal layer, and an opening provided in the patterned region of the transparent conductive layer.Type: ApplicationFiled: November 28, 2007Publication date: February 4, 2010Inventors: Yoshitaka Kinoshita, Atsushi Shiraishi, Toshihiko Satou, Hiroyuki Tsukada
-
Publication number: 20100011158Abstract: A memory controller for performing processing for writing data in an interleaved manner and in units of pages in a semiconductor memory section made up of chip 0 and chip 1, each of the chips composed of a large number of memory cells capable of storing two-bit data in one memory cell in units of two types of pages, the memory controller including a NAND I/F with the semiconductor memory section, and a CPU configured to execute writing programs repeatedly for two types of pages in a memory cell which belongs to the chip 0 and thereafter execute writing programs into a memory cell which belongs to the chip 1.Type: ApplicationFiled: July 10, 2009Publication date: January 14, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsushi SHIRAISHI, Toshihiko KITAZUME
-
Patent number: 7603957Abstract: A thread cutting device includes a thread catching member having a catching portion, wherein the thread catching member moves back and forth across a path of a lower thread reeled out from a bobbin so as to catch the lower thread by the catching portion and cuts the lower thread by cooperating with a fixed knife, a first power transmitting portion which transmits a power to the thread catching member, a first cam member provided on a lower shaft rotated by a sewing machine motor and transmits a first moving force to the thread catching member through the first power transmitting portion, a second power transmitting portion which transmits a second moving force from a stepping motor to the thread catching member through the first power transmitting portion.Type: GrantFiled: October 2, 2007Date of Patent: October 20, 2009Assignee: Juki CorporationInventor: Atsushi Shiraishi
-
Patent number: 7583265Abstract: An image display method for displaying, after imaging, a plurality of image data each relating to attribute data, includes: disposing a reference image object for indication of each of the plurality of image data at a position based on any one of the corresponding attribute data in a virtual horizontal plane in a virtual three-dimensional (3D) space; selecting one or more of the image data from the plurality of image data; disposing a viewing image object for indication of the selected image data at a position of any of the corresponding reference image objects moved in a direction of a normal or a substantially normal to the virtual horizontal plane; setting a field of view in the virtual 3D space; and imaging the virtual 3D space in the field of view set in the setting the field of view.Type: GrantFiled: July 27, 2006Date of Patent: September 1, 2009Assignee: Seiko Epson CorporationInventors: Atsushi Shiraishi, Shinji Hattori, Yosuke Wakamiya, Shinji Kumakiri
-
Publication number: 20090189309Abstract: A laminated rotor core (36) wherein permanent magnets (47) are inserted in respective magnet insertion holes (46) is disposed between and pressed by an upper die (37) and a lower die (29). The upper die (37) has resin reservoir pots (50) provided above the laminated rotor core (36) and at positions corresponding to the respective magnet insertion holes (46). Raw resin material put in the resin reservoir pots (50) is heated by the upper die (37). Subsequently, the resin material in a liquefied state is ejected from the resin reservoir pots (50) by plungers (52) that are inserted and moves vertically in the resin reservoir pots (50) and is directly filled in the magnet insertion holes (46). Consequently, the respective magnet insertion holes (46) are filled with the resin material more evenly and highly reliable products can be supplied at low cost.Type: ApplicationFiled: January 16, 2006Publication date: July 30, 2009Applicant: MITSUI HIGH-TEC, INC.Inventors: Satoshi Matsubayashi, Hirotoshi Mabu, Katsumi Amano, Atsushi Shiraishi
-
Publication number: 20090187703Abstract: In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.Type: ApplicationFiled: March 26, 2009Publication date: July 23, 2009Inventors: HIDEFUMI OODATE, Atsushi Shiraishi, Shigeo Kurakata, Kunihiro Katayama, Motoki Kanamori
-
Publication number: 20090181721Abstract: A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#1 through #13) are disposed on a card substrate (1) in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit (3) and an SIM (Subscriber Identity Module) card unit (4) are respectively connected and mounted to predetermined terminals of the connector terminals (#1 through #13). The memory card unit (3) and the SIM card unit (4) are respectively separately provided with areas for storing secret codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level. Owing to the adoption of a plural-column layout corresponding to a form typified by the zigzag fashion in an array of the connector terminals, a relatively simple structure can be adopted in a card slot.Type: ApplicationFiled: March 23, 2009Publication date: July 16, 2009Inventors: Hirotaka NISHIZAWA, Haruji ISHIHARA, Atsushi SHIRAISHI, Yosuke YUKAWA
-
Patent number: 7552876Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.Type: GrantFiled: October 25, 2007Date of Patent: June 30, 2009Assignee: Renesas Technology Corp.Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa
-
Patent number: 7549086Abstract: In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.Type: GrantFiled: October 23, 2007Date of Patent: June 16, 2009Assignees: Renesas Technology Corp., Hitachi ULSI Sytems Co., Ltd.Inventors: Hidefumi Oodate, Atsushi Shiraishi, Shigeo Kurakata, Kunihiro Katayama, Motoki Kanamori
-
Patent number: 7516903Abstract: A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#1 through #13) are disposed on a card substrate (1) in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit (3) and an SIM (Subscriber Identity Module) card unit (4) are respectively connected and mounted to predetermined terminals of the connector terminals (#1 through #13). The memory card unit (3) and the SIM card unit (4) are respectively separately provided with areas for storing secret codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level. Owing to the adoption of a plural-column layout corresponding to a form typified by the zigzag fashion in an array of the connector terminals, a relatively simple structure can be adopted in a card slot.Type: GrantFiled: April 7, 2006Date of Patent: April 14, 2009Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Yosuke Yukawa
-
Publication number: 20090019210Abstract: The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.Type: ApplicationFiled: September 10, 2008Publication date: January 15, 2009Inventors: Shinsuke Asari, Chiaki Shinagawa, Yasuhiro Nakamura, Motoki Kanamori, Atsushi Shiraishi