Patents by Inventor Atsushi Shiraishi

Atsushi Shiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7197595
    Abstract: A nonvolatile memory has plural memory blocks, each having a plurality of sub memory blocks, and is capable of programming to a first sub memory block within a first memory block and a second sub memory block within a second memory block in parallel. The first sub memory block has a management area for storing a management information including linking information between the first sub memory block corresponding sub memory blocks of other memory blocks. A control circuit controls reading the linking information from the first sub memory block in accordance with address information, and programming to the first sub memory block in accordance with the address information and corresponding sub memory blocks by the linking information.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: March 27, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Shinsuke Asari, Takayuki Tamura, Atsushi Shiraishi
  • Publication number: 20070033334
    Abstract: A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition.
    Type: Application
    Filed: October 3, 2006
    Publication date: February 8, 2007
    Inventors: Kunihiro Katayama, Motoki Kanamori, Atsushi Shikata, Hidefumi Oodate, Atsushi Shiraishi
  • Publication number: 20070030283
    Abstract: An image display method for displaying, after imaging, a plurality of image data each relating to attribute data, includes: disposing a reference image object for indication of each of the plurality of image data at a position based on any one of the corresponding attribute data in a virtual horizontal plane in a virtual three-dimensional (3D) space; selecting one or more of the image data from the plurality of image data; disposing a viewing image object for indication of the selected image data at a position of any of the corresponding reference image objects moved in a direction of a normal or a substantially normal to the virtual horizontal plane; setting a field of view in the virtual 3D space; and imaging the virtual 3D space in the field of view set in the setting the field of view.
    Type: Application
    Filed: July 27, 2006
    Publication date: February 8, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Atsushi SHIRAISHI, Shinji HATTORI, Yosuke WAKAMIYA, Shinji KUMAKIRI
  • Publication number: 20060278146
    Abstract: A threading device for a sewing machine includes a needle bar provided with a guide member having a stopper portion, a threading shaft having a threading member, operation means having a guide groove formed in a spiral shape with respect to a rotating axis of the threading shaft, and a pin, which is fixed to the threading shaft, having both ends protruded outward in a radial direction with respect to the threading shaft. One end of the pin penetrates the geode groove while the other end of the pin engages with the stopper portion. The threading device further includes erroneous rotation preventing means which prevents the threading shaft from rotating in when the threading shaft moves downward, and permits the threading shaft to rotate when the second end of the pin engages with the stopper portion.
    Type: Application
    Filed: May 26, 2006
    Publication date: December 14, 2006
    Applicant: Juki Corporation
    Inventor: Atsushi Shiraishi
  • Patent number: 7140795
    Abstract: The printer can improve the workability of storing and ejecting printing sheets in or from a storage tray. The printer includes a storage tray comprising a sheet storage case for storing a stack of a plurality of printing sheets with at least one of the sides of the storage case being opened and a cover for covering the sheet storage case, wherein the cover comprises a cover body and an moveable member supported by the cover body for freely opening and closing the opening of the sheet storage case. When the entire storage tray is disposed in the slot of the chassis, a pick-up block ejects one printing sheet at a time, and when a part of the storage tray is pulled out of the slot of the chassis, the moveable member can be opened or closed and the printing sheet can be stored in or discharged from the sheet storage case.
    Type: Grant
    Filed: November 28, 2003
    Date of Patent: November 28, 2006
    Assignee: Sony Corporation
    Inventors: Atsushi Shiraishi, Tomohiro Maekawa, Masatoshi Mikuriya
  • Patent number: 7133961
    Abstract: A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: November 7, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kunihiro Katayama, Motoki Kanamori, Atsushi Shikata, Hidefumi Oodate, Atsushi Shiraishi
  • Publication number: 20060233032
    Abstract: When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.
    Type: Application
    Filed: June 16, 2006
    Publication date: October 19, 2006
    Inventors: Motoki Kanamori, Kunihiro Katayama, Atsushi Shiraishi, Shigeo Kurakata, Atsushi Shikata
  • Publication number: 20060228910
    Abstract: A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#1 through #13) are disposed on a card substrate (1) in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit (3) and an SIM (Subscriber Identity Module) card unit (4) are respectively exclusively connected and mounted to predetermined terminals of the connector terminals (#1 through #13). The memory card unit (3) and the SIM card unit (4) are respectively separately provided with areas for storing secrete codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level.
    Type: Application
    Filed: June 9, 2006
    Publication date: October 12, 2006
    Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Yosuke Yukawa
  • Publication number: 20060228909
    Abstract: A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#1 through #13) are disposed on a card substrate (1) in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit (3) and an SIM (Subscriber Identity Module) card unit (4) are respectively exclusively connected and mounted to predetermined terminals of the connector terminals (#1 through #13). The memory card unit (3) and the SIM card unit (4) are respectively separately provided with areas for storing secrete codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level.
    Type: Application
    Filed: June 9, 2006
    Publication date: October 12, 2006
    Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Yosuke Yukawa
  • Patent number: 7104714
    Abstract: A printer includes a transporting block, a printing block, a positioning block, and an intermediate picking-up device. The positioning block is disposed between the transporting block and the printing block, and positions printing sheets transported by the transporting block at a predetermined location one at a time, so that they are positioned one at a time at a printing location of the printing block where printing is performed on the printing sheets. The intermediate picking-up means picks up the printing sheets positioned at the predetermined location in the positioning block one at a time in order to transport the printing sheets to the printing block.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: September 12, 2006
    Assignee: Sony Corporation
    Inventors: Tomohiro Maekawa, Teruyasu Hanagami, Shogo Fujito, Atsushi Shiraishi
  • Publication number: 20060197729
    Abstract: For statically driving a liquid-crystal optical-modulation device, an alternating electric field produced by a drive signal is applied to a liquid crystal included therein. In a first period in which the alternating electric field has a first polarity, the drive signal is pulse-width modulated based on a first ON-voltage and a first OFF-voltage. In a second period in which the alternating electric field has a second polarity, the drive signal is pulse-width modulated based on a second ON-voltage and a second OFF-voltage.
    Type: Application
    Filed: March 6, 2006
    Publication date: September 7, 2006
    Inventors: Atsushi Shiraishi, Masafumi Ide
  • Patent number: 7102943
    Abstract: When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: September 5, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Motoki Kanamori, Kunihiro Katayama, Atsushi Shiraishi, Shigeo Kurakata, Atsushi Shikata
  • Publication number: 20060183355
    Abstract: A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#1 through #13) are disposed on a card substrate (1) in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit (3) and an SIM (Subscriber Identity Module) card unit (4) are respectively connected and mounted to predetermined terminals of the connector terminals (#1 through #13). The memory card unit (3) and the SIM card unit (4) are respectively separately provided with areas for storing secret codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level. Owing to the adoption of a plural-column layout corresponding to a form typified by the zigzag fashion in an array of the connector terminals, a relatively simple structure can be adopted in a card slot.
    Type: Application
    Filed: April 7, 2006
    Publication date: August 17, 2006
    Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Yosuke Yukawa
  • Patent number: 7080604
    Abstract: A lower thread supplying apparatus for a sewing machine has a bobbin accommodating portion 11 for detachably accommodating a lower thread bobbin 12 from an opening part 101c, a tension applying portion 13 for hitching a lower thread, a lower thread cutting knife 14 provided at the end portion of a lower thread passing route with a predetermined length, a cover 15 for covering the opening part 101c, a cover plate 20 for covering around the lower thread bobbin 12, a bending portion 16, a first guide portion 30 for introducing the lower thread to the bending portion and a second guide portion 40 for introducing the lower thread to the lower thread cutting knife. The bobbin accommodating portion, the tension applying portion, the bending portion and the lower thread cutting knife are provided at an inner area of the opening part 101c.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: July 25, 2006
    Assignee: Juki Corporation
    Inventors: Kuniharu Sakuma, Yumiko Kotaki, legal representative, Atsushi Shiraishi, Hiroshi Kotaki, deceased
  • Publication number: 20060157572
    Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.
    Type: Application
    Filed: March 20, 2006
    Publication date: July 20, 2006
    Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa
  • Publication number: 20060157573
    Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.
    Type: Application
    Filed: March 20, 2006
    Publication date: July 20, 2006
    Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa
  • Patent number: 7070113
    Abstract: A nonvolatile memory has an erase table in which a free-space information flag is associated with each physical address of a memory area and an address translation table in which a physical address of a memory area is associated with each logical address. The free-space information flag indicates whether a corresponding memory area is permitted to be erased. A control circuit determines a memory area to which rewrite data is to be written by referring to the free-space information flag, reflects the physical address and the logical address of the memory area to which the data is written into the address translation table, and updates the free-space information flag. The memory area to which rewrite data is to be written is determined by referring to the free-space information flag, and rewriting is not performed in the same memory area.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: July 4, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Atsushi Shiraishi, Takayuki Tamura, Chiaki Kumahara, Shinsuke Asari
  • Patent number: 7061812
    Abstract: Disclosed is a memory card which ensures high-speed data writing operations. The memory card is formed of an erasable and programmable nonvolatile memory and a control circuit. A memory array of the nonvolatile memory has an erasing table including a first flag designating whether a memory area is a vacant area or not in every erasing unit. The control circuit exercises, when the number of memory areas in which the erasable data is written becomes a constant value, pre-erasing control to previously erase the erasable data over the memory area depending on the first flag indicating a vacant area. Since the erasing process is previously executed to the vacant memory area, necessity for insertion of the erasing process just before the writing process using the vacant memory area can be reduced and thereby writing data to the memory card can be highly speeded.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: June 13, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Chiaki Shinagawa, Motoki Kanamori, Atsushi Shiraishi
  • Patent number: 7055757
    Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: June 6, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa
  • Patent number: 7048197
    Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: May 23, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa