Patents by Inventor Atsushi Sugahara

Atsushi Sugahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5600461
    Abstract: An active matrix type liquid crystal display device having an array substrate for allowing parasitic capacitances formed between a pixel electrode and scan and signal lines disposed in the vicinity thereof to be remarkably decreased.
    Type: Grant
    Filed: June 14, 1995
    Date of Patent: February 4, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomomasa Ueda, Masahiko Akiyama, Atsushi Sugahara, Makoto Shibusawa, Mitsushi Ikeda, Yoshiko Tsuji, Hisao Toeda
  • Patent number: 5563432
    Abstract: In a thin-film transistor 171, in order to sufficiently suppress an optical leakage current Ioff, thereby achieving a high ON/OFF current ratio, at least one of shortest distances between an arbitrary intersection of an outline of a gate electrode 131 and an outline of a drain electrode 141 and an intersection of the outline of the gate electrode 131 and an outline of a source electrode 151 is formed to be larger than the shortest distance between a portion of the outline of the gate electrode 131 overlapping the drain electrode 141 and another portion thereof overlapping the source electrode 151.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: October 8, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasunori Miura, Makoto Shibusawa, Atsushi Sugahara, Masahiro Seiki
  • Patent number: 5459596
    Abstract: An active matrix type liquid crystal display device having a plurality of scan lines, a plurality of signal lines intersected with the plurality of scan lines, the plurality of scan lines being insulated from the plurality of signal lines, a thin film transistor element having a gate portion and a drain portion and disposed at each intersection of the plurality of scan lines and the plurality of signal lines, the gate portion being connected to a scan line at the intersection, the drain portion being connected to a signal line at the intersection, an array substrate formed in the intersection and having a pixel electrode, the pixel electrode being electrically connected to the source portion of the thin film transistor element, an opposite substrate having an opposite electrode opposed to the array substrate, a liquid crystal layer disposed between the array substrate and the opposite substrate, and a shield electrode disposed on the array substrate, the shield electrode being overlaid through an insulation l
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: October 17, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomomasa Ueda, Masahiko Akiyama, Atsushi Sugahara, Makoto Shibusawa, Mitsushi Ikeda, Yoshiko Tsuji, Hisao Toeda
  • Patent number: 5391243
    Abstract: A wire for electric railways comprises a copper alloy which consists essentially, by weight percent, of 0.1 to 1.0% Cr, 0.01 to 0.3% Zr, and 10 ppm or less O, and if required, further contains at least one element selected from the group consisting of 0.01 to 0.1% Si and 0.001 to 0.05% Mg, with the balance being Cu and inevitable impurities. The wire is manufactured by hot working a copper alloy billet having the above composition, immediately quenching the hot worked billet to prepare an element wire, cold working the element wire at least once, and subjecting the cold worked element wire to aging treatment.
    Type: Grant
    Filed: October 28, 1993
    Date of Patent: February 21, 1995
    Assignees: Mitsubishi Materials Corporation, Railway Technical Research Institute
    Inventors: Motoo Goto, Shizuo Kawakita, Yoshiharu Mae, Takuro Iwamura, Yutaka Koshiba, Kenji Yajima, Syunji Ishibashi, Hiroki Nagasawa, Atsushi Sugahara, Sumihisa Aoki, Haruhiko Asao