Patents by Inventor Atsushi Suwa

Atsushi Suwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040242182
    Abstract: An object is to provide an antenna switch semiconductor integrated circuit which reduces a consumption current. To this end, of two control input signals which are fed to a logic circuit which controls turning on and off of a plurality of switching FETs, a control input signal for switching between a sending mode and a receiving mode is fed to an oscillation circuit, thereby making the oscillation circuit operate only during the sending mode under which the logic circuit needs a high voltage. A voltage raising circuit accordingly operates, whereby a raised voltage is supplied to the logic circuit. During the receiving mode, the oscillation circuit stops, and the voltage raising circuit stops. With a switch turned on using the logic circuit, a power source voltage is supplied directly to the logic circuit when the voltage raising circuit is not in operation. This shortens the operation time of the voltage raising circuit and reduces the consumption current.
    Type: Application
    Filed: March 17, 2004
    Publication date: December 2, 2004
    Inventors: Kenichi Hidaka, Tadayoshi Nakatsuka, Atsushi Suwa
  • Publication number: 20030116780
    Abstract: In order that the DC potential of the input terminal does not rise, whereby ON/OFF switching is accordingly performed normally, even when a signal having a large amplitude is inputted to an input terminal, thereby the depletion layer expands due to electron trapping effect, a first field effect transistor is connected between a first switch input terminal and a first switch output terminal in a manner that the source is arranged on the first switch input terminal side, a second field effect transistor is connected between the first switch output terminal and a second switch input terminal in a manner that the source is arranged on the second switch input terminal side, a third field effect transistor is connected between the second switch input terminal and a second switch output terminal in a manner that the source is arranged on the second switch input terminal side, and a fourth field effect transistor is connected between the second switch output terminal and the first switch input terminal in a manner th
    Type: Application
    Filed: December 19, 2002
    Publication date: June 26, 2003
    Inventors: Atsushi Suwa, Tadayoshi Nakatsuka, Tadashi Komatsu, Katsushi Tara