Patents by Inventor Atsushi Tominaga

Atsushi Tominaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020014893
    Abstract: There is provided a displacement measuring apparatus efficiently productive and easily applicable to high precise measurement of displacement with contact probe detection for hardly-measurable works in the art such as micro-works and deep parts in complicated structures. A scale member includes a spindle and a scale both supported by a parallel leaf spring movable on a scale substrate. The spindle is arranged in coaxial with a measurement axis in the scale member. The L & S slit-processed scale is integrated with the spindle and supported by the parallel leaf spring to move together with the spindle along the measurement axis. The spindle, scale and parallel leaf spring are coupled to the scale substrate interposing an anchor of the parallel leaf spring therebetween. The spindle, scale and parallel leaf spring are formed in an integral structure and only the anchor contacts the scale substrate while the spindle, scale and parallel leaf spring slightly float from the scale substrate.
    Type: Application
    Filed: July 19, 2001
    Publication date: February 7, 2002
    Applicant: Mitutoyo Corporation
    Inventors: Toshitaka Shimomura, Atsushi Tominaga
  • Publication number: 20020008325
    Abstract: An implementation base (10) is formed of a silicon substrate (11) having a recess (12) on a surface. Wire layers (13) are formed on the silicon substrate (11), continuously extending from the bottom of and via the side of the recess (12) to the top surface. A semiconductor chip (14) is implemented in the recess (12) of the implementation base (10) in a flip-chip manner to configure a functional device unit.
    Type: Application
    Filed: May 10, 2001
    Publication date: January 24, 2002
    Applicant: MITUTOYO CORPORATION
    Inventor: Atsushi Tominaga
  • Publication number: 20010053578
    Abstract: A semiconductor device including a capacitor element which has a high withstand voltage, a large capacitance, and little parasitic resistance and parasitic capacitance. On interlayer insulating films provided on a semiconductor device, there is formed a lower electrode of a capacitor element coated with an alumina thin film through use of a portion of a first metal layer to be used for forming a first wiring layer. An electrode to constitute a portion of an upper electrode of the capacitor element is formed from a second metal layer so as to come into contact with the alumina thin film provided on the surface of the lower electrode. On the electrode, an upper electrode of the capacitor element is formed through use of a portion of a third metal layer to be used for forming a second wiring layer. Further, an lead electrode connected to the lower electrode is formed through use of a portion of the third metal layer by removal of a portion of the alumina thin film provided on the surface of the lower electrode.
    Type: Application
    Filed: July 10, 2001
    Publication date: December 20, 2001
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Atsushi Tominaga
  • Publication number: 20010038292
    Abstract: A transmission electrode 10 and a detection electrode 12 are placed in an electrode section of a sensor and are capacity-coupled with a reception electrode placed on an opposed scale. Capacity change between the transmission electrode 10 and the reception electrode caused by displacement is detected with the detection electrode 12. A plurality of signals different in phase are supplied to the transmission electrode 10. The signal lines are wired like a zigzag using an upper layer and a lower layer and the distances between the signal lines and the detection electrode 12 are made substantially equal for making uniform the crosstalk amounts relative to the detection electrode 12.
    Type: Application
    Filed: December 4, 2000
    Publication date: November 8, 2001
    Applicant: Mitutoyo Corporation
    Inventors: Kenichi Nakayama, Toshihiro Hasegawa, Atsushi Tominaga
  • Patent number: 6278172
    Abstract: A semiconductor device including a capacitor element which has a high withstand voltage, a large capacitance, and little parasitic resistance and parasitic capacitance. On interlayer insulating films provided on a semiconductor device, there is formed a lower electrode of a capacitor element coated with an alumina thin film through use of a portion of a first metal layer to be used for forming a first wiring layer. An electrode to constitute a portion of an upper electrode of the capacitor element is formed from a second metal layer so as to come into contact with the alumina thin film provided on the surface of the lower electrode. On the electrode, an upper electrode of the capacitor element is formed through use of a portion of a third metal layer to be used for forming a second wiring layer. Further, an lead electrode connected to the lower electrode is formed through use of a portion of the third metal layer by removal of a portion of the alumina thin film provided on the surface of the lower electrode.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: August 21, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Atsushi Tominaga
  • Patent number: 5831328
    Abstract: A semiconductor device in which at least one IIL transistor is formed, the semiconductor device having, a base region (6) provided against a semiconductor substrate (1), a plurality of collector regions (9) formed in the base region (6), each of the collector regions (9) aligning in a direction parallel to a spreading surface of the semiconductor substrate (1), and a metal wiring having a plurality of contact portions (10), each of the contact portions being connected electrically to predetermined one of the collector regions (9), characterized in that, each of the contact portions of the metal wiring (10) is connected electrically to the collector region (9) corresponding thereto via a polysilicon cap (11) formed so as to cover the collector region (9).
    Type: Grant
    Filed: July 9, 1997
    Date of Patent: November 3, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Fumitoshi Yamamoto, Atsushi Tominaga