Abstract: The invention provides a spin qubit-type semiconductor device capable of achieving both high-speed spin manipulation and high integration, and an integrated circuit for the spin qubit-type semiconductor device.

Abstract: To suppress a leakage current caused by a gate of a tunnel field effect transistor included in a silicon spin quantum bit device, the silicon spin quantum bit device is provided including a tunnel field effect transistor having a gate, a source, and a drain, a quantum gate operation mechanism for spin control, which is provided under the tunnel field effect transistor, and an inter-qubit coupler for coupling a channel of the tunnel field effect transistor with a channel of a tunnel field effect transistor included in another quantum bit device. Further, the gate is made wider in width than the channel and is partly formed on the inter-qubit coupler.

Abstract: [Problem to be Solved] To provide a fluorescent probe for ALDH3A1 detection that can be used in flow cytometry adaptable to live cells. [Means of Resolution] A compound represented by general formula (I) or a salt thereof, wherein the compound or salt thereof has a retention time on an HPLC chromatogram measured under the following conditions of longer than 6.9 minutes when said compound is in aldehyde form and of 6.9 minutes or less when said compound is in carboxylic acid form.

Abstract: A semiconductor device includes a semiconductor layer, first gate electrode, second gate electrode, first conductive layer and second conductive layer. The semiconductor layer includes a first side surface, a second side surface, a first end portion, and a second end portion. The first side surface and the second side surface face each other. The first end portion and the second end portion face each other. A first gate insulating layer is provided between the first gate electrode and the first side surface. A second gate insulating layer is provided between the second gate electrode and the second side surface. A first metal oxide layer is provided between the first conductive layer and the first end portion. A second metal oxide layer is provided between the second conductive layer and the second end portion.

Abstract: According to one embodiment, the contact electrode extends in the inter-layer insulating layer toward the second semiconductor region. The metal silicide film is in contact with the second semiconductor region and the contact electrode. The metal silicide film includes a first part and a second part. The first part is provided between a bottom of the contact electrode and the second semiconductor region. The second part is provided on a surface of the second semiconductor region between the first part and the gate electrode. A bottom of the second part is located at a position shallower than a bottom the first part.

Abstract: According to one embodiment, the contact electrode extends in the inter-layer insulating layer toward the second semiconductor region. The metal silicide film is in contact with the second semiconductor region and the contact electrode. The metal silicide film includes a first part and a second part. The first part is provided between a bottom of the contact electrode and the second semiconductor region. The second part is provided on a surface of the second semiconductor region between the first part and the gate electrode. A bottom of the second part is located at a position shallower than a bottom the first part.

Abstract: A semiconductor device has two first semiconductor regions that are arranged at intervals on a surface of a semiconductor substrate, one of the two semiconductor regions being a source region and another of the two semiconductor regions being a drain region, and a contact that extends from at least one of the two first semiconductor regions on the semiconductor substrate. The contact comprises a single-crystal first semiconductor layer arranged to contact the surface of the semiconductor substrate, a compound layer that is arranged on the first semiconductor layer and includes a semiconductor in the first semiconductor layer and a metal, and a metal layer arranged on the compound layer.

Abstract: A semiconductor storage device includes a semiconductor substrate; an active region provided in the semiconductor substrate and extending in a first direction; and a plurality of gates provided above the active region and extending in a second direction. The gates are provided with a stack of a floating gate and a control gate, and an elevated portion is provided above the active region disposed between adjacent gates.

Abstract: According to one embodiment, a semiconductor device includes an active area that is formed on a semiconductor substrate, a trench that isolates the active area, a nitride film that is buried in the trench, an air gap that is formed above the nitride film along the trench, and a gate electrode that is formed on the active area to span the trench through the air gap.

Abstract: A fin type semiconductor layer is formed on a substrate with a source and a drain. A dummy gate is formed crossing the fin type semiconductor layer. After depositing an insulating film on the dummy gate, the upper surface of the dummy gate is exposed. The dummy gate is then removed to form a gate trench. On the surface of the fin type semiconductor layer in the gate trench, a gate insulating film is formed. Material for a gate electrode is filled in the gate trench and etched to form the gate electrode. The height of the upper surface of the gate electrode is equal to or lower than the height of the upper surface of the fin type semiconductor layer at the source and the drain, and is equal to or higher than the height of the upper surface of the fin type semiconductor layer in the gate trench.

Abstract: The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of Fins including a semiconductor material on an insulation layer; forming gate insulation films on sidewalls of the Fins; forming a gate electrode which extends in a direction of arrangement of the Fins and which is electrically insulated from the Fins, the gate electrode is common in the Fins on the gate insulation film; implanting an impurity into portions of the Fins by using the gate electrode as a mask to form a source-drain diffusion layer, the portions of the Fins extending on both sides of the gate electrodes; and depositing a conductive material on both sides of the Fins to connect the Fins to each other.

Abstract: Multi-gate metal oxide silicon transistors and methods of making multi-gate metal oxide silicon transistors are provided. The multi-gate metal oxide silicon transistor contains a bulk silicon substrate containing one or more convex portions between shallow trench regions; one or more dielectric portions over the convex portions; one or more silicon fins over the dielectric portions; a shallow trench isolation layer in the shallow trench isolation regions; and a gate electrode. The upper surface of the shallow trench isolation layer can be located below the upper surface of the convex portion, or the upper surface of the shallow trench isolation layer can be located between the lower surface and the upper surface of first dielectric layer. The multi-gate metal oxide silicon transistor can contain second spacers adjacent to side surfaces of the convex portions in a source/drain region.

Abstract: According to one embodiment, gate electrodes of a multi-gate field effect transistors and methods of making a gate electrode of a multi-gate field effect transistor are provided. The gate electrode can contain a semiconductor substrate; a dielectric layer over the semiconductor substrate; a fin over the dielectric layer; a gate insulating layer over the side surfaces of the fin; a gate electrode layer over the fin; and a polysilicon layer over the fin. The gate electrode does not contain a gate insulating layer over the upper surface of the dielectric layer except portions of the upper surface of the dielectric layer that contact with the side surfaces of the gate insulating layer formed over the side surface of the fin. In another embodiment, the gate electrode can contain an oxygen diffusion barrier layer or a first oxygen diffusion layer over the upper surface of the dielectric layer.

Abstract: There is provided a semiconductor device including: convex semiconductor layers formed on a semiconductor substrate via an insulating film; gate electrodes formed on a pair of facing sides of the semiconductor layers via a gate insulating film; a channel region formed of silicon between the gate electrodes in the semiconductor layers; a source extension region and a drain extension region formed of silicon germanium or silicon carbon on both sides of the channel region in the semiconductor layers; and a source region formed of silicon so as to adjoin to the opposite side of the channel region in the source extension region, and a drain region formed of silicon so as to adjoin to the opposite side of the channel region in the drain extension region in the semiconductor layers.

Abstract: The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.

Abstract: The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.

Abstract: Multi-gate metal oxide silicon transistors and methods of making multi-gate metal oxide silicon transistors are provided. The multi-gate metal oxide silicon transistor contains a bulk silicon substrate containing one or more convex portions between shallow trench regions; one or more dielectric portions over the convex portions; one or more silicon fins over the dielectric portions; a shallow trench isolation layer in the shallow trench isolation regions; and a gate electrode. The upper surface of the shallow trench isolation layer can be located below the upper surface of the convex portion, or the upper surface of the shallow trench isolation layer can be located between the lower surface and the upper surface of first dielectric layer. The multi-gate metal oxide silicon transistor can contain second spacers adjacent to side surfaces of the convex portions in a source/drain region.

Abstract: This disclosure concerns a manufacturing method of a semiconductor device includes forming a Fin-type body on an insulation layer, the Fin-type body being made of a semiconductor material and having an upper surface covered with a protective film; forming a gate insulation film on side surfaces of the Fin-type body; depositing a gate electrode material so as to cover the Fin-type body; planarizing the gate electrode material; forming a gate electrode by processing the gate electrode material; depositing an interlayer insulation film so as to cover the gate electrode; exposing the upper surface of the gate electrode; depositing a metal layer on the upper surface of the gate electrode; siliciding the gate electrode by reacting the gate electrode with the metal layer; forming a trench on the upper surface of the protective film by removing an unreacted metal in the metal layer; and filling the trench with a conductor.

Abstract: A line-form insulator is formed on a substrate and then the substrate is etched with the insulator used as a mask to form first trenches on both sides of the insulator. Side wall insulators are formed on the side walls of the first trenches, the substrate is etched with the insulator and side wall insulators used as a mask to form second trenches in the bottom of the first trenches. After, the substrate is oxidized with the insulator and side wall insulators used as an anti-oxidation mask to cause oxide regions formed on the adjacent side walls of the second trenches lying on both sides of the substrate to make contact with each other and the insulator and side wall insulators are removed. Then, a fin FET having a semiconductor region as a line-form fin is formed in the substrate.