Patents by Inventor Atul Garg
Atul Garg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11303576Abstract: A network device receives a fragmented packet of an internet protocol (IP) packet. The fragmented packet is subsequently received relative to an initial fragmented packet of the IP packet and includes a first set of tuple information. The network device determines an entry of a hash table associated with the IP packet, based on the first set of tuple information and a fragment identifier (ID) within the fragmented packet. The network device retrieves a second set of tuple information associated with the fragmented packet from the hash table entry, and transmits an indication of the first and second sets of tuple information.Type: GrantFiled: October 17, 2019Date of Patent: April 12, 2022Assignee: Cisco Technology, Inc.Inventors: Ajay K. Modi, Atul Garg, Murukanandam K. Panchalingam, Umamaheswararao Karyampudi, Munish Mehta
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Publication number: 20210119925Abstract: A network device receives a fragmented packet of an internet protocol (IP) packet. The fragmented packet is subsequently received relative to an initial fragmented packet of the IP packet and includes a first set of tuple information. The network device determines an entry of a hash table associated with the IP packet, based on the first set of tuple information and a fragment identifier (ID) within the fragmented packet. The network device retrieves a second set of tuple information associated with the fragmented packet from the hash table entry, and transmits an indication of the first and second sets of tuple information.Type: ApplicationFiled: October 17, 2019Publication date: April 22, 2021Inventors: Ajay K. MODI, Atul GARG, Murukanandam K. PANCHALINGAM, Umamaheswararao KARYAMPUDI, Munish MEHTA
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Patent number: 10491904Abstract: Video pixel line buffers are widely used for data processing in video codecs. Video data may be packed into buffers configured to store a plurality of words, each word comprising a series of bits. The video data may be associated with two or more channels. In order to reduce realization costs, data blocks from two different channels may be packed from opposite sides of a word in the buffer in opposite directions. In some embodiments, data blocks from two or more physical channels may be mapped to two or more virtual channels, the virtual channels having balanced data block sizes. The data blocks associated with the virtual channels may then be packed to one or more buffers.Type: GrantFiled: January 18, 2019Date of Patent: November 26, 2019Assignee: QUALCOMM IncorporatedInventors: Shu Lin, Mang Li, Kai Wang, Atul Garg
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Publication number: 20190174135Abstract: Video pixel line buffers are widely used for data processing in video codecs. Video data may be packed into buffers configured to store a plurality of words, each word comprising a series of bits. The video data may be associated with two or more channels. In order to reduce realization costs, data blocks from two different channels may be packed from opposite sides of a word in the buffer in opposite directions. In some embodiments, data blocks from two or more physical channels may be mapped to two or more virtual channels, the virtual channels having balanced data block sizes. The data blocks associated with the virtual channels may then be packed to one or more buffers.Type: ApplicationFiled: January 18, 2019Publication date: June 6, 2019Inventors: Shu Lin, Mang Li, Kai Wang, Atul Garg
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Patent number: 10277904Abstract: Video pixel line buffers are widely used for data processing in video codecs. Video data may be packed into buffers configured to store a plurality of words, each word comprising a series of bits. The video data may be associated with two or more channels. In order to reduce realization costs, data blocks from two different channels may be packed from opposite sides of a word in the buffer in opposite directions. In some embodiments, data blocks from two or more physical channels may be mapped to two or more virtual channels, the virtual channels having balanced data block sizes. The data blocks associated with the virtual channels may then be packed to one or more buffers.Type: GrantFiled: August 28, 2015Date of Patent: April 30, 2019Assignee: QUALCOMM IncorporatedInventors: Shu Lin, Mang Li, Kai Wang, Atul Garg
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Patent number: 10111782Abstract: The present invention is directed to a resorbable hemostatic nonwoven felt suitable for use in laparoscopic procedures and to methods for manufacturing said felt.Type: GrantFiled: March 6, 2017Date of Patent: October 30, 2018Assignee: Ethicon, Inc.Inventors: Benjamin D. Fitz, Dwayne Looney, Thomas Lee Craven, Clifford Dey, Atul Garg
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Patent number: 9883183Abstract: A method and apparatus for determining neighborhood video attribute values for a frame of video data are disclosed. In one aspect, the method includes receiving coordinates for a current block location and a previous block location of the frame and generating a vector indicative of the displacement of the current block from the previous block via comparing the coordinates of the current block location to the coordinates of the previous block location. The method may also include updating the neighborhood video attribute values based at least in part on the generated vector and processing the frame based on the updated neighborhood video attribute values.Type: GrantFiled: November 23, 2015Date of Patent: January 30, 2018Assignee: QUALCOMM IncorporatedInventors: Gaurang Chaudhari, Atul Garg
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Publication number: 20170172805Abstract: The present invention is directed to a resorbable hemostatic nonwoven felt suitable for use in laparoscopic procedures and to methods for manufacturing said felt.Type: ApplicationFiled: March 6, 2017Publication date: June 22, 2017Inventors: Benjamin D. Fitz, Dwayne Looney, Thomas Lee Craven, Clifford Dey, Atul Garg
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Publication number: 20170150144Abstract: A method and apparatus for determining neighborhood video attribute values for a frame of video data are disclosed. In one aspect, the method includes receiving coordinates for a current block location and a previous block location of the frame and generating a vector indicative of the displacement of the current block from the previous block via comparing the coordinates of the current block location to the coordinates of the previous block location. The method may also include updating the neighborhood video attribute values based at least in part on the generated vector and processing the frame based on the updated neighborhood video attribute values.Type: ApplicationFiled: November 23, 2015Publication date: May 25, 2017Inventors: Gaurang Chaudhari, Atul Garg
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Publication number: 20170064308Abstract: Video pixel line buffers are widely used for data processing in video codecs. Video data may be packed into buffers configured to store a plurality of words, each word comprising a series of bits. The video data may be associated with two or more channels. In order to reduce realization costs, data blocks from two different channels may be packed from opposite sides of a word in the buffer in opposite directions. In some embodiments, data blocks from two or more physical channels may be mapped to two or more virtual channels, the virtual channels having balanced data block sizes. The data blocks associated with the virtual channels may then be packed to one or more buffers.Type: ApplicationFiled: August 28, 2015Publication date: March 2, 2017Inventors: Shu Lin, Mang Li, Kai Wang, Atul Garg
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Patent number: 9432674Abstract: Multi-level prediction mode encoding type decision methods and systems are presented. In one embodiment, an indication of a prediction mode level is received and encoding is performed in accordance with said prediction mode level. The indication of said prediction mode level is programmable and can be set at different levels. The prediction mode level can be associated with a programmable encoding type decision point (e.g., early, intermediate, late, etc.). The encoding process includes deciding upon an I-type or P-type encoding. In one embodiment, a multi-stage encoding type method is also implemented in intra-prediction related search and inter-prediction related search and respective corresponding prediction operations are performed, wherein at least a portion of the intra-prediction related search and the inter-prediction related search are performed in parallel.Type: GrantFiled: February 2, 2009Date of Patent: August 30, 2016Assignee: NVIDIA CORPORATIONInventors: Atul Garg, Thomas Karpati
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Patent number: 8923385Abstract: Described herein are a number of approaches for implementing a video encoder with hardware-enabled rewind functionality. In several embodiments, rewind functionality can be implemented in hardware, in a manner which allows the transform engine of the encoder to reprocess video data, without requesting data from other stages in the encoder. Such rewind functionality is useful in implementing some video standards in a pipeline architecture, such as the H.264 standard. In one embodiment, a method of encoding video data is described, which involves obtaining a first portion of video data from a first location in a buffer, and performing an encoding operation on it. The second portion of video data is obtained from a second location in the buffer, and encoding operations begin on the second portion. The first portion of video data can be retrieved from the first location, in order to reprocess the first portion if necessary.Type: GrantFiled: May 1, 2008Date of Patent: December 30, 2014Assignee: Nvidia CorporationInventors: Atul Garg, Prahlad Venkatapuram
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Patent number: 8831099Abstract: Non-encoded data for a macroblock of an image frame is accessed. A cost to intra-encode the macroblock is computed using at least a portion of the non-encoded data in place of reconstructed image data from another macroblock of the image frame. The cost can be compared against the cost to inter-encode the first macroblock in order to select how the first macroblock is to be encoded.Type: GrantFiled: December 17, 2008Date of Patent: September 9, 2014Assignee: Nvidia CorporationInventors: Manindra Parhy, Atul Garg, Prahlad Venkatapuram, Chung-Cheng Lou, Ignatius Tjandrasuwita
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Patent number: 8761253Abstract: The following embodiments describe an approach for selecting an intra prediction mode for video encoding, such as occurs in the H.264 standard. One embodiment describes a method of selecting an optimum intra prediction mode. This method involves selecting a first intra prediction mode, which is used to determine a search order for a number of intra prediction modes. These intra prediction modes are then evaluated in order to identify the optimum intra prediction mode.Type: GrantFiled: May 28, 2008Date of Patent: June 24, 2014Assignee: NVIDIA CorporationInventors: Atul Garg, Thomas Karpati, Jackson Lee, Ignatius Tjandrasuwita
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Patent number: 8705630Abstract: Described are methods and systems for processing data. A motion estimator uses a block of an input frame of video data and a block of a reference frame of video data to generate motion vectors according to a first encoding scheme. A motion compensator produces half pel motion vectors from the motion vectors according to a second encoding scheme that is different from the first encoding scheme.Type: GrantFiled: December 8, 2006Date of Patent: April 22, 2014Assignee: NVIDIA CorporationInventors: Derek Pappas, Atul Garg, Shankar Moni, Harikrishna M. Reddy, Matthew R. Longnecker, Christopher L. Mills, Ignatius B. Tjandrasuwita
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Patent number: 8681861Abstract: Described herein are a number of approaches for implementing a multistandard video encoder. In several embodiments, a single encoder supports multiple video encoding standards via dedicated hardware datapaths, while using shared buffers to store a video data between processing stages. In one such embodiment, system for video encoding is described. The system includes a number of encoding stages, for performing tasks associated with encoded video data. The system also includes a number of encoding buffers, coupled to the encoding stages, for storing video data between encoding stages. The encoding stages are operable to encode the video data in accordance with a number of video encoding standards, and the encoding buffers are operable to store partially encoded video data, regardless of the video encoding standard selected.Type: GrantFiled: May 1, 2008Date of Patent: March 25, 2014Assignee: Nvidia CorporationInventors: Atul Garg, Anil Sharma
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Patent number: 8666181Abstract: The present invention facilitates efficient and effective detection of pixel alteration. In one embodiment a pixel alteration analysis system includes a difference summing multiple engine component and a control component. The difference summing multiple engine component determines the sum of differences between pixel values in a plurality of pixels. The control component determines an indication of motion based upon said relationship of said pixels in said plurality of pixels. In one exemplary implementation, the difference in values corresponds to a relationship between values of pixels in a block of pixels at different frames. The number and configuration of pixels in a block partition can be flexibly changed.Type: GrantFiled: December 10, 2008Date of Patent: March 4, 2014Assignee: Nvidia CorporationInventors: Prahlad Venkatapuram, Atul Garg, Karunakar Rachamreddy, Visalakshi Vaduganathan, Manindra Parhy, Ignatius Tjandrasuwita
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Patent number: 8526601Abstract: In the present method of implementing functioning of an encryption engine, a plurality of logic blocks are provided, each for running a function. Each function is run based on three variables, each of which may have a first or second value. The function is run with the first variable value selected as having its first value, and with the second and third variables having their actual values. The function is again run with the first variable value selected as having its second value, and again with the second and third variables having their actual values. An actual value of the first variable is determined, and the output of the logic block is determined by the actual value of the first variable.Type: GrantFiled: April 5, 2004Date of Patent: September 3, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Atul Garg, Siaw-Kang Lai
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Patent number: 8495230Abstract: A wireless local area network (WLAN) includes at least one hybrid coordinator (HC) and at least one Quality of Service Station (QSTA). The HC transmits a schedule frame element (SEF). The WLAN also includes a clocking mechanism that sets a substantially absolute start time of a service interval. A method of synchronizing the HC and the QSTA includes transmitting a schedule element frame (SEF), and setting a substantially absolute start-time of a service interval, and a first transmitted frame element.Type: GrantFiled: March 5, 2004Date of Patent: July 23, 2013Assignee: Koninklijke Philips N.V.Inventors: Atul Garg, Javier Del Prado Pavon, Sai Shankar, Amjad Soomro, Zhun Zhong
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Patent number: 8437405Abstract: The present invention includes a method and system for encoding video data by accessing a picture to be encoded, wherein the picture comprises a plurality of macro-blocks. A plurality of programmable counters are associated with each macro-block to be encoded. A counter associated with a macro-block of the plurality of macro-blocks is accessed and a value of the counter is determined. The method further includes determining whether to encode the macro-block as an Intra or non-Intra based on the value of the counter. If the macro-block is encoded as Intra, its counter is reset. If the macro-block is encoded as non-Intra, its counter value is updated. The counter value may be reset with a random number. Counters can be programmed such that a region of interest is defined for updating associated macro-blocks with greater frequency.Type: GrantFiled: December 8, 2004Date of Patent: May 7, 2013Assignee: Nvidia CorporationInventors: Iole Moccagatta, Atul Garg, Shankar Moni, Dipankar Talukdar, Ignatius B. Tjandrasuwita, Sandeep Shyamsukha