Abstract: Signal edge sharpener circuitry is operably connected to the word lines in a memory array to pull up a rising edge of a signal on the word line and/or to pull down a falling edge of the signal on the word line. Pulling the signal up and/or down reduces the amount of time the word line is asserted and reduces the amount of time between precharge operations.

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit may include a memory array with a plurality of memory cells, first logic circuitry, first switching circuitry, first latch circuitry, and second switching circuitry. The first logic circuitry may be configured to generate a first bit line pre-charge signal for a first memory cell of the plurality of memory cells, where the first bit line pre-charge signal is generated in response to a sleep signal. The first switching circuitry may be configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal. The first latch circuit may receive the sleep signal and the first bit line pre-charge signal and generate a delayed sleep signal.

Abstract: A memory circuit includes first and second word line drivers coupled to a control circuit configured to output clock pulse signals, first and second I/O circuits coupled to the control circuit and configured to output first through fourth pulse signals responsive to the clock pulse signals, first through forth memory arrays coupled to the first and second word line drivers and first and second I/O circuits, a first booster circuit coupled to the first I/O circuit and first and second memory arrays and configured to couple first and second memory array word lines to a power supply node responsive to the respective first and second pulse signals, and a second booster circuit coupled to the second I/O circuit and third and fourth memory arrays and configured to couple third and fourth memory array word lines to the power supply node responsive to the respective third and fourth pulse signals.

Abstract: A memory device includes a memory array that includes one or more rows of memory cells and one or more columns of memory cells. The comparator circuitry is operably connected to at least one column of memory cells in the one or more columns of memory cells. The comparator circuitry includes a precompute circuit and a select circuit operably connected to the outputs of the precompute circuit. The precompute circuit is operable to precompute a comparison operation to produce a first precompute signal and a second precompute signal. The select circuit is operable to receive a first cell data signal from a memory cell in the column of memory cells. Based at least on the first cell data signal, the select circuit selects either the first precompute signal or the second precompute signal to output from the comparator circuitry as a signal read from the memory cell.

Abstract: Systems and methods are provided a memory circuit that provides multiple clock signals to a local clock driver. One of the clock signals may be faster than the other and, as a result, at least one transistor of the local clock driver may be turned on early to improve the delay of the rising edge, the falling edge, or both edges of the slower clock signal. The local clock driver may include a first transistor electrically connected to the NAND gate and a second transistor electrically connected to the NOR gate. As a result of the additional, faster clock signal, a reduction of the clock to word line time in the memory circuit can be achieved.

Abstract: Systems and methods are provided for limiting a negative bit line voltage in a SRAM cell. A voltage limiter circuit may be implemented in a write driver to control the magnitude of negative voltage imposed on a bit line. The voltage limiter circuit can produce the required magnitude of negative bit line voltage at lower operating voltage levels. The voltage limiter circuit can also limit the magnitude of negative bit line voltage to not exceed a predetermined value. The reduction of the magnitude of the negative bit line voltage can reduce the active power of a SRAM cell.

Abstract: A memory device includes a memory array that includes one or more rows of memory cells and one or more columns of memory cells. The comparator circuitry is operably connected to at least one column of memory cells in the one or more columns of memory cells. The comparator circuitry includes a precompute circuit and a select circuit operably connected to the outputs of the precompute circuit. The precompute circuit is operable to precompute a comparison operation to produce a first precompute signal and a second precompute signal. The select circuit is operable to receive a first cell data signal from a memory cell in the column of memory cells. Based at least on the first cell data signal, the select circuit selects either the first precompute signal or the second precompute signal to output from the comparator circuitry as a signal read from the memory cell.

Abstract: A memory circuit includes a plurality of word lines, a word line driver coupled to a first end of the plurality of word lines and configured to activate each word line of the plurality of word lines, a local I/O circuit configured to generate a pulse signal corresponding to the word line driver activating any word line of the plurality of word lines, a first node configured to carry a first power supply voltage, and a booster circuit coupled to a second end of the plurality of word lines, the local I/O circuit, and the first node. The booster circuit is configured to couple each word line of the plurality of word lines to the first node responsive to the pulse signal and to the corresponding word line being activated by the word line driver.

Abstract: The present disclosure provides a memory device, which includes a memory array, a read-clock generation circuit, and a local input/output circuit. The read-clock generation circuit receives a sense amplifier enable signal, a first sense amplifier pre-charge signal, and a latched write enable signal to generate a first read enable signal. The local input/output circuit includes multiple pairs of column-address pass gates, and a pair of read pass gates. The plurality of pairs of column-address pass gates are configured to receive data from a bit-line pair of the memory cells in a row selected by an address signal. The pair of read pass gates connects a read bit-line pair to the bit-line pair in response to the first read enable signal being in a low-logic state. The first read enable signal is de-asserted after the read bit-line pair connected to the pair of read pass gates are pre-charged.

Abstract: Devices, circuits, and methods are provided. A circuit comprises a tracking word line circuit that is configured to receive an internal clock signal, a turbo signal, and a read enable signal, and to generate a first tracking reading signal and a first tracking writing signal in response to the internal clock signal the turbo signal, and the write enable signal. The circuit also comprises a tracking bit line circuit configured to receive the first tracking reading signal and the first tracking writing signal, wherein the tracking bit line circuit is configured to generate a tracking bit line signal in response to the first tracking reading signal and the first tracking writing signal, wherein the tracking word line circuit is configured to generate a reset signal in response to the tracking bit line signal and transmit the reset signal to the clock generator.

Abstract: A semiconductor device includes a memory bank. The memory bank includes a plurality N of memory arrays and a local control circuit. Each memory array includes a plurality of bit cells configured to store bits of information and connected between a plurality of bit lines and a plurality of complement bit lines. The local control circuit is configured to pre-charge the bit lines and the complement bit lines at most N?1 memory array at a time. A method of operating the semiconductor device is also disclosed.

Abstract: Memory clock drivers, memories, and methods of operating memory clock drivers are provided. A memory device contains two memory clock drivers disposed opposite each other across an array of rows of memory cells. The memory clock drivers contain decoders, which decode an address corresponding to one or more rows of memory cells. The decoders are configured to decode the address to provide a plurality of word line signals to the corresponding rows of memory cells. The memory device also includes a row select circuit, which receives a row select address and activates a corresponding row of memory cells. The memory device includes control circuitry to control the arrays of memory cells at a local and a global level, as well as I/O modules to send signals to different parts of the memory device and integrate the memory device into external devices.

Abstract: Systems and methods are provided for limiting a negative bit line voltage in a SRAM cell. A voltage limiter circuit may be implemented in a write driver to control the magnitude of negative voltage imposed on a bit line. The voltage limiter circuit can produce the required magnitude of negative bit line voltage at lower operating voltage levels. The voltage limiter circuit can also limit the magnitude of negative bit line voltage to not exceed a predetermined value. The reduction of the magnitude of the negative bit line voltage can reduce the active power of a SRAM cell.

Abstract: Circuits and methods are provided for a clock generation circuit that includes a first transistor, wherein a gate of the first transistor is connected to a clock signal, a second transistor, connected in parallel to the first transistor, and a driving circuit, coupled to the second transistor, and comprising an input and an output, wherein the input of the driving circuit is connected to the clock signal, the output of the driving circuit is connected to a gate of the second transistor, and the driving circuit is configured to reduce a slew of the clock signal.

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

Abstract: A semiconductor device includes a memory bank. The memory bank includes a plurality N of memory arrays and a local control circuit. Each memory array includes a plurality of bit cells configured to store bits of information and connected between a plurality of bit lines and a plurality of complement bit lines. The local control circuit is configured to pre-charge the bit lines and the complement bit lines at most N?1 memory array at a time. A method of operating the semiconductor device is also disclosed.

Abstract: A memory circuit includes a global control circuit, a first local control circuit and a first set of word line post-decoder circuits. The global control circuit is configured to generate a first and second set of global pre-decoder signals and a first set of local address signals. The first local control circuit includes a first set of repeater circuits and a first clock pre-decoder circuit. The first set of repeater circuits is configured to generate a first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and a second set of local pre-decoder signals in response to the second set of global pre-decoder signals. The first clock pre-decoder circuit is configured to generate a first and second set of clock signals. The first set of word line post-decoder circuits is configured to generate a first set of word line signals.

Abstract: A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.

Abstract: Memory clock drivers, memories, and methods of operating memory clock drivers are provided. A memory device contains two memory clock drivers disposed opposite each other across an array of rows of memory cells. The memory clock drivers contain decoders, which decode an address corresponding to one or more rows of memory cells. The decoders are configured to decode the address to provide a plurality of word line signals to the corresponding rows of memory cells. The memory device also includes a row select circuit, which receives a row select address and activates a corresponding row of memory cells. The memory device includes control circuitry to control the arrays of memory cells at a local and a global level, as well as I/O modules to send signals to different parts of the memory device and integrate the memory device into external devices.

Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in an array, an input/output (I/O) interface connected to the plurality of memory cells to output data signal from each memory cell, and a control circuit. In some embodiments, the control circuit includes a first clock generator to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal and provide the first clock signal to the plurality of memory cells. In some embodiments, the control circuit includes a second clock generator to generate a third clock signal according to the input clock signal and a DFT (design for testability) enable signal. In some embodiments, the control circuit generates an output clock signal according to the second clock signal or the third clock signal.