Abstract: A semiconductor device includes a memory bank. The memory bank includes a plurality N of memory arrays and a local control circuit. Each memory array includes a plurality of bit cells configured to store bits of information and connected between a plurality of bit lines and a plurality of complement bit lines. The local control circuit is configured to pre-charge the bit lines and the complement bit lines at most N?1 memory array at a time. A method of operating the semiconductor device is also disclosed.

Abstract: A memory circuit may comprise a memory array, a first tracking cell, a second tracking cell, a first tracking circuit, and a second tracking circuit. A first portion of the memory array may comprise a plurality of first nominal memory cells coupled to a first bit line segment extending along a first lateral direction. A second portion of the memory array may comprise a plurality of second nominal memory cells coupled to a second bit line segment and a third bit line segment both extending along the first lateral direction. The first tracking circuit can be configured to activate the first tracking cell, in response to at least one of the first nominal memory cells being selected. The second tracking circuit can be configured to activate the second tracking cell, in response to at least one of the second nominal memory cells being selected.

Abstract: An example memory device includes a repair cell in a repair column having a repair local bit line, a repair local input/output (LIO) circuit having an input connected to the repair local bit line and an output connected to a repair global bit line, and a plurality of memory cells arranged in a first plurality of columns. The memory device further includes a memory LIO circuit and a first global input/output (GIO) circuit having a first multiplexer with a first input connected to the memory global bit line, a second input connected to receive the output of the repair LIO circuit, an output terminal, and a select signal terminal. The first GIO circuit further includes a first compare circuit.

Abstract: A memory circuit includes a plurality of word lines, a word line driver and a booster circuit. The word line driver is configured to drive a first end of a word line of the plurality of word lines to each of a high logical state or a low logical state in response to a word line signal. The booster circuit is configured to drive a second end of the word line of the plurality of word lines to each of the high logical state or the low logical state in response to the word line signal. The booster circuit is configured to drive the second end of the word line of the plurality of word lines concurrently with the word line driver driving the first end of the word line of the plurality of word lines to the respective high logical state or low logical state.

Abstract: A sensing circuit and a control method of the sensing circuit are provided. The sensing circuit includes a data line, a complementary data line, a read bit line, a complementary read bit line, a read pass gate circuit. The read pass gate circuit connects the data line to the read bit line and connect the complementary data line to the complementary read bit line when a voltage level on the read bit line and a voltage level on the complementary read bit line are pre-charged to a first voltage level.

Abstract: A memory device includes a plurality of memory cells arranged in an array, a first clock generator connected to the plurality of memory cells and configured to generate a local clock signal to be provided to the plurality of memory cells, a second clock generator connected to an input/output interface connected to the plurality of memory cells, the second clock generator configured to generate a global clock signal to be provided to the input/output interface, and one or more logic gates connected to at least one of the first clock generator or the second clock generator, wherein the one or more logic gates allow the local clock signal and the global clock signal to be output independently.

Abstract: A memory circuit may comprise a memory array, a first tracking cell, a second tracking cell, a first tracking circuit, and a second tracking circuit. A first portion of the memory array may comprise a plurality of first nominal memory cells coupled to a first bit line segment extending along a first lateral direction. A second portion of the memory array may comprise a plurality of second nominal memory cells coupled to a second bit line segment and a third bit line segment both extending along the first lateral direction. The first tracking circuit can be configured to activate the first tracking cell, in response to at least one of the first nominal memory cells being selected. The second tracking circuit can be configured to activate the second tracking cell, in response to at least one of the second nominal memory cells being selected.

Abstract: A sensing circuit and a control method of the sensing circuit are provided. The sensing circuit includes a data line, a complementary data line, a read bit line, a complementary read bit line, a read pass gate circuit and logic circuit. The logic circuit enables the read pass gate circuit when a voltage level on the read bit line and a voltage level on the complementary read bit line are pre-charged to a first voltage level, and disable the read pass gate circuit when one of the voltage level on the read bit line and the voltage level on the complementary read bit line is pull to a second voltage level different from the first voltage level. The read pass gate circuit is enabled to connect the data line to the read bit line and connect the complementary data line to the complementary read bit line.

Abstract: A memory circuit includes first and second word line drivers coupled to a control circuit configured to output clock pulse signals, first and second I/O circuits coupled to the control circuit and configured to output first through fourth pulse signals responsive to the clock pulse signals, first through forth memory arrays coupled to the first and second word line drivers and first and second I/O circuits, a first booster circuit coupled to the first I/O circuit and first and second memory arrays and configured to couple first and second memory array word lines to a power supply node responsive to the respective first and second pulse signals, and a second booster circuit coupled to the second I/O circuit and third and fourth memory arrays and configured to couple third and fourth memory array word lines to the power supply node responsive to the respective third and fourth pulse signals.

Abstract: A memory circuit may comprise at least one of: a first memory bank, a first local input/output (I/O) circuit, a second memory bank, a second local I/O circuit, a global I/O circuit, a first local latch circuit, and a second local latch circuit. The first memory bank may include a first memory array. The second memory bank may include a second memory array. The first local latch circuit can be configured to be activated to latch data bit when read from the first memory array. The second local latch circuit can be configured to be activated to latch data bit when read from the second memory array. The first local latch circuit and the second local latch circuit can be configured to be alternately activated.

Abstract: A memory device includes a memory bank with a memory cell connected to a local bit line and a word line. A first local data latch is connected to the local bit line and has an enable terminal configured to receive a first local clock signal. A word line latch is configured to latch a word line select signal, and has an enable terminal configured to receive a second local clock signal. A first global data latch is connected to the first local data latch by a global bit line, and the first global data latch has an enable terminal configured to receive a global clock signal. A global address latch is connected to the word line latch and has an enable terminal configured to receive the global clock signal. A bank select latch is configured to latch a bank select signal, and has an enable terminal configured to receive the second local clock signal.

Abstract: A memory device includes a substrate. A transistor is over a front side of the substrate. A front side interconnect structure is over the front side of the substrate and electrically connected with the transistor. A storage element is at a position below the transistor and electrically connected with the transistor, wherein the storage element comprises a first electrode, a second electrode, and a data storage layer between the first electrode and the second electrode.

Abstract: A sensing circuit and a control method of the sensing circuit are provided. The sensing circuit includes a data line, a complementary data line, a read bit line, a complementary read bit line, a read pass gate circuit and logic circuit. The logic circuit enables the read pass gate circuit when a voltage level on the read bit line and a voltage level on the complementary read bit line are pre-charged to a first voltage level, and disable the read pass gate circuit when one of the voltage level on the read bit line and the voltage level on the complementary read bit line is pull to a second voltage level different from the first voltage level. The read pass gate circuit is enabled to connect the data line to the read bit line and connect the complementary data line to the complementary read bit line.

Abstract: A memory device includes a memory bank with a memory cell connected to a local bit line and a word line. A first local data latch is connected to the local bit line and has an enable terminal configured to receive a first local clock signal. A word line latch is configured to latch a word line select signal, and has an enable terminal configured to receive a second local clock signal. A first global data latch is connected to the first local data latch by a global bit line, and the first global data latch has an enable terminal configured to receive a global clock signal. A global address latch is connected to the word line latch and has an enable terminal configured to receive the global clock signal. A bank select latch is configured to latch a bank select signal, and has an enable terminal configured to receive the second local clock signal.

Abstract: A memory device includes a plurality of memory cells arranged in an array, a first clock generator connected to the plurality of memory cells and configured to generate a local clock signal to be provided to the plurality of memory cells, a second clock generator connected to an input/output interface connected to the plurality of memory cells, the second clock generator configured to generate a global clock signal to be provided to the input/output interface, and one or more logic gates connected to at least one of the first clock generator or the second clock generator, wherein the one or more logic gates allow the local clock signal and the global clock signal to be output independently.

Abstract: Systems and methods are provided for a memory device including a first memory array, a local input/output (LIO) circuit, and a global input/output (GIO) circuit. The first memory array includes a memory cell and a local bit line. The LIO circuit is configured to receive a local bit line signal on the local bit line and to generate a global bit line signal on a global bit line based on the local bit line signal. The GIO circuit is coupled to the LIO circuit and is configured to receive the global bit line signal. The GIO circuit comprises a latch circuit including a global bit line signal latch that is configured to latch the global bit line signal, and a booster circuit that is configured to drive the global bit line signal in the GIO circuit based on a previous global bit line signal.

Abstract: A memory circuit includes a first local control circuit and a first set of word line post-decoder circuits. The first local control circuit includes a first set of repeater circuits and a first clock pre-decoder circuit. The first set of repeater circuits is configured to generate a first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and a second set of local pre-decoder signals in response to the second set of global pre-decoder signals. The first clock pre-decoder circuit is configured to generate a first and second set of clock signals in response to a first set of local address signals. The first set of word line post-decoder circuits is configured to generate a first set of word line signals in response to the first set of clock signals, and the first and second set of local pre-decoder signals.

Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.

Abstract: A memory device includes a plurality of memory cells arranged in an array, a first clock generator connected to the plurality of memory cells and configured to generate a local clock signal to be provided to the plurality of memory cells, a second clock generator connected to an input/output interface connected to the plurality of memory cells, the second clock generator configured to generate a global clock signal to be provided to the input/output interface, and one or more logic gates connected to at least one of the first clock generator or the second clock generator, wherein the one or more logic gates allow the local clock signal and the global clock signal to be output independently.

Abstract: A memory circuit includes a global control circuit, a first local control circuit and a first set of word line post-decoder circuits. The global control circuit is configured to generate a first and second set of global pre-decoder signals and a first set of local address signals. The first local control circuit includes a first set of repeater circuits and a first clock pre-decoder circuit. The first set of repeater circuits is configured to generate a first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and a second set of local pre-decoder signals in response to the second set of global pre-decoder signals. The first clock pre-decoder circuit is configured to generate a first and second set of clock signals. The first set of word line post-decoder circuits is configured to generate a first set of word line signals.