Abstract: A memory circuit includes a plurality of word lines, a word line driver coupled to the plurality of word lines, and a booster circuit coupled to the plurality of word lines. The word line driver is configured to output a first word line signal on a first word line of the plurality of word lines, and the booster circuit includes a first node configured to carry a first power supply voltage and is configured to couple the first word line of the plurality of word lines to the first node responsive to a pulse signal and the first word line signal.

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

Abstract: Disclosed herein are related to reducing power consumption of a memory device when transitioning from a sleep state to an operational state. In one aspect, the memory device includes a memory cell to store data. In one aspect, the memory device includes an output driver configured to: generate an output signal indicating the stored data, in response to a sleep tracking signal indicating that the memory cell is in the operational state, and generate the output signal having a predetermined voltage irrespective of the stored data, in response to the sleep tracking signal indicating that the memory cell is in the sleep state. In one aspect, the sleep tracking signal is delayed from a sleep control signal causing the memory cell to operate in the sleep state or the operational state.

Abstract: A memory circuit includes a global control circuit, a first local control circuit, and a first set of word line post-decoder circuits coupled to a first set of memory cells that is configured to store a first set of data. The global control circuit is configured to generate a first and second set of global pre-decoder signals, and a first set of local address signals. The first local control circuit includes a first set of repeater circuits and a first clock pre-decoder circuit. The first set of repeater circuits is configured to generate a first and second set of local pre-decoder signals in response to the corresponding first and second set of global pre-decoder signals. The first clock pre-decoder circuit is configured to generate a first and second set of clock signals in response to the first set of local address signals and the first clock signal.

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

Abstract: A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.

Abstract: Systems and methods are provided for limiting a negative bit line voltage in a SRAM cell. A voltage limiter circuit may be implemented in a write driver to control the magnitude of negative voltage imposed on a bit line. The voltage limiter circuit can produce the required magnitude of negative bit line voltage at lower operating voltage levels. The voltage limiter circuit can also limit the magnitude of negative bit line voltage to not exceed a predetermined value. The reduction of the magnitude of the negative bit line voltage can reduce the active power of a SRAM cell.

Abstract: A semiconductor device includes a memory bank and first and second clock generators. The first clock generator includes a first transistor configured to receive an external clock signal. The first clock generator is configured to generate a global clock signal that is based on the external clock signal and that controls writing to and reading from the memory bank. The second clock generator includes a first transistor configured to receive the external clock signal. The second clock generator is configured to generate a pipeline clock signal that is based on the external clock signal and that controls a pipeline operation of reading from the memory bank. Methods of operating the first and second clock generators are also disclosed.

Abstract: A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.

Abstract: A memory device includes a memory array that includes one or more rows of memory cells and one or more columns of memory cells. The comparator circuitry is operably connected to at least one column of memory cells in the one or more columns of memory cells. The comparator circuitry includes a precompute circuit and a select circuit operably connected to the outputs of the precompute circuit. The precompute circuit is operable to precompute a comparison operation to produce a first precompute signal and a second precompute signal. The select circuit is operable to receive a first cell data signal from a memory cell in the column of memory cells. Based at least on the first cell data signal, the select circuit selects either the first precompute signal or the second precompute signal to output from the comparator circuitry as a signal read from the memory cell.

Abstract: Memory clock drivers, memories, and methods of operating memory clock drivers are provided. A memory device contains two memory clock drivers disposed opposite each other across an array of rows of memory cells. The memory clock drivers contain decoders, which decode an address corresponding to one or more rows of memory cells. The decoders are configured to decode the address to provide a plurality of word line signals to the corresponding rows of memory cells. The memory device also includes a row select circuit, which receives a row select address and activates a corresponding row of memory cells. The memory device includes control circuitry to control the arrays of memory cells at a local and a global level, as well as I/O modules to send signals to different parts of the memory device and integrate the memory device into external devices.

Abstract: A memory device includes a memory bank with a memory cell connected to a local bit line and a word line. A first local data latch is connected to the local bit line and has an enable terminal configured to receive a first local clock signal. A word line latch is configured to latch a word line select signal, and has an enable terminal configured to receive a second local clock signal. A first global data latch is connected to the first local data latch by a global bit line, and the first global data latch has an enable terminal configured to receive a global clock signal. A global address latch is connected to the word line latch and has an enable terminal configured to receive the global clock signal. A bank select latch is configured to latch a bank select signal, and has an enable terminal configured to receive the second local clock signal.

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit may include a memory array with a plurality of memory cells, first logic circuitry, first switching circuitry, first latch circuitry, and second switching circuitry. The first logic circuitry may be configured to generate a first bit line pre-charge signal for a first memory cell of the plurality of memory cells, where the first bit line pre-charge signal is generated in response to a sleep signal. The first switching circuitry may be configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal. The first latch circuit may receive the sleep signal and the first bit line pre-charge signal and generate a delayed sleep signal.

Abstract: A memory device includes a memory array that includes one or more rows of memory cells and one or more columns of memory cells. The comparator circuitry is operably connected to at least one column of memory cells in the one or more columns of memory cells. The comparator circuitry includes a precompute circuit and a select circuit operably connected to the outputs of the precompute circuit. The precompute circuit is operable to precompute a comparison operation to produce a first precompute signal and a second precompute signal. The select circuit is operable to receive a first cell data signal from a memory cell in the column of memory cells. Based at least on the first cell data signal, the select circuit selects either the first precompute signal or the second precompute signal to output from the comparator circuitry as a signal read from the memory cell.

Abstract: A memory device includes a memory bank with a memory cell connected to a local bit line and a word line. A first local data latch is connected to the local bit line and has an enable terminal configured to receive a first local clock signal. A word line latch is configured to latch a word line select signal, and has an enable terminal configured to receive a second local clock signal. A first global data latch is connected to the first local data latch by a global bit line, and the first global data latch has an enable terminal configured to receive a global clock signal. A global address latch is connected to the word line latch and has an enable terminal configured to receive the global clock signal. A bank select latch is configured to latch a bank select signal, and has an enable terminal configured to receive the second local clock signal.

Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit may include a memory array with a plurality of memory cells, first logic circuitry, first switching circuitry, first latch circuitry, and second switching circuitry. The first logic circuitry may be configured to generate a first bit line pre-charge signal for a first memory cell of the plurality of memory cells, where the first bit line pre-charge signal is generated in response to a sleep signal. The first switching circuitry may be configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal. The first latch circuit may receive the sleep signal and the first bit line pre-charge signal and generate a delayed sleep signal.

Abstract: A memory device Input/Output includes a memory cell having a local bit line. A first IO circuit is coupled to the local bit line and is configured to output a local IO signal to a global bit line. A second IO circuit is coupled to the global bit line and is configured to output a global IO signal. A latch circuit is configured to latch the local IO signal in response to a data signal on the local bit line.

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit may include a memory array with a plurality of memory cells, first logic circuitry, first switching circuitry, first latch circuitry, and second switching circuitry. The first logic circuitry may be configured to generate a first bit line pre-charge signal for a first memory cell of the plurality of memory cells, where the first bit line pre-charge signal is generated in response to a sleep signal. The first switching circuitry may be configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal. The first latch circuit may receive the sleep signal and the first bit line pre-charge signal and generate a delayed sleep signal.