Abstract: A circuit comprises a first memory cell, a second memory cell, and a disturb control circuit. The first memory cell has a first port and a second port. The first port is associated with a first write assist circuit. The second port is associated with a second write assist circuit. The second memory cell has a third port and a fourth port. The third port is associated with a third write assist circuit. The fourth port is associated with a fourth write assist circuit. The disturb control circuit is configured to selectively turn on at least one of the first write assist circuit, the second write assist circuit, the third write assist circuit, or the fourth write assist circuit according to whether the first port, the second port, the third port, or the fourth port is determined to be write disturbed.

Abstract: A memory circuit includes a memory cell, a first bit line, a first bit line bar, a sense amplifier, a first switch and a second switch. The memory cell is coupled with a first bit line having a first bit line portion and a second bit line portion. The first bit line bar has a first bit line bar portion and a second bit line bar portion. The sense amplifier includes a read/write circuit configured to couple the second bit line portion to a global bit line. The first switch is coupled between the first bit line bar portion and the second bit line bar portion. The second switch is coupled between the first bit line portion and the second bit line portion.

Abstract: A circuit includes a first set of transistors and a second set of transistors. The first set of transistors is configured to be turned on in a sequential manner. The second set of transistors is configured to be turned on in a sequential manner after the first set of transistors is turned on. A transistor of the first set of transistors corresponds to a first time delay. The first set of transistors corresponds to a second time delay that is a multiple of the first time delay.

Abstract: A memory macro includes a plurality of columns and a plurality of switching circuits. A column of the plurality of columns has a plurality of voltage supply nodes corresponding to a plurality of memory cells in the column. A switching circuit of the plurality of switching circuits corresponds to a column of the plurality of columns and is configured to selectively provide a first voltage value of a first voltage source or a second voltage value of a second voltage source to the voltage supply nodes. The first voltage value and the second voltage value differ by a predetermined voltage value.

Abstract: A circuit includes a memory cell having a first control line and a second control line, the first control line carrying a first control signal, the second control line carrying a second control signal. A first circuit is coupled to the first control line, the second control line, and a node, and a second circuit is coupled to the node and responds to a timing of the first control signal and the second control signal. The first circuit and the second circuit, based on the first control signal and the second control signal, are configured to generate a node signal on the node, and a logical value of the node signal indicates a write disturb condition of the memory cell.

Abstract: A circuit comprises a memory cell, a first circuit, and a second circuit. The memory cell has a first control line and a second control line. The first control line carries a first control signal. The second control line carries a second control signal. The first circuit is coupled with the first control line, the second control line, and a node. The second circuit is coupled to the node and is configured to receive a first clock signal and a second clock signal. The first circuit and the second circuit, based on the first control signal, the second control signal, the first clock signal and the second clock signal, are configured to generate a node signal on the node. A logical value of the node signal indicates a write disturb condition of the memory cell.

Abstract: A memory circuit includes at least one first memory cell of a first memory array for storing a first datum. The at least one first memory cell is coupled with a first word line and a first bit line. A first bit line bar is disposed substantially parallel with the first bit line. A first switch is coupled between a sense amplifier and the first bit line bar. The first switch can electrically isolate the sense amplifier from the first bit line bar if the sense amplifier is capable of sensing a first voltage difference between the first bit line. The first bit line bar and the first voltage difference is substantially equal to or larger than a predetermined value.

Abstract: A circuit comprises a memory cell, a first circuit, and a second circuit. The memory cell has a first control line and a second control line. The first control line carries a first control signal. The second control line carries a second control signal. The first circuit is coupled with the first control line, the second control line, and a node. The second circuit is coupled to the node and is configured to receive a first clock signal and a second clock signal. The first circuit and the second circuit, based on the first control signal, the second control signal, the first clock signal and the second clock signal, are configured to generate a node signal on the node. A logical value of the node signal indicates a write disturb condition of the memory cell.

Abstract: A circuit includes a memory cell, a first data line, a second data line, and a clamping unit. The memory cell includes a data node, a first pass gate, and a second pass gate. The first pass gate is between the first data line and the data node. The second pass gate is between the second data line and the data node. The clamping unit is electrically coupled to the first data line and configured to pull a voltage level of the first data line toward a clamped voltage level when the clamping unit is enabled, and to function as an open circuit to the first data line when the clamping unit is disabled. The clamping unit is disabled when a first control signal indicates that a voltage level of the second data line is pulled toward a reference voltage level.

Abstract: A circuit comprises a first memory cell, a second memory cell, and a disturb control circuit. The first memory cell has a first port and a second port. The first port is associated with a first write assist circuit. The second port is associated with a second write assist circuit. The second memory cell has a third port and a fourth port. The third port is associated with a third write assist circuit. The fourth port is associated with a fourth write assist circuit. The disturb control circuit is configured to selectively turn on at least one of the first write assist circuit, the second write assist circuit, the third write assist circuit, or the fourth write assist circuit according to whether the first port, the second port, the third port, or the fourth port is determined to be write disturbed.

Abstract: A device layout tool includes a gate electrode layer, wherein the gate electrode layer is configured to define a three dimensional gate structure over a fin structure, wherein the fin structure has three exposed surfaces. The device layout tool further includes a defect-describing layer, wherein the defect-describing layer is configured to define locations of gate defects relative to the three exposed surfaces of the fin structure.

Abstract: A circuit includes a first memory cell and a data control circuit configured to provide first data and second data. The first memory cell has a first port and a second port. The first data is written from the first port to the first memory cell. The second data is based on information of the first data. The second port is configured to write the second data to the first memory cell based on a detection of a write disturb caused by the second port to the first port.

Abstract: A memory macro comprises a plurality of memory cells, a plurality of first amplifying circuits, a first driver circuit, and a first level shifter. The plurality of memory cells is arranged in groups of a first direction and groups of a second direction. Each amplifying circuit is coupled to a plurality of first memory cells arranged in a first group of the first direction via a first data line. The first driver circuit is configured to drive the plurality of first amplifying circuits. The first level shifter is configured to level shift an input signal operating in a first power domain to an output signal operating in a second power domain. The output signal of the first level shifter is for use by the first driver circuit. The first driver circuit and a sense amplifier of an amplifying circuit operate in the second power domain.

Abstract: A sense amplifier comprises a cross coupled pair of inverters, a first transistor, a second transistor, and a capacitive device. The cross coupled pair of inverters includes a first end, a second end, and a third end. The first end is configured to receive a first supply voltage. The second end is coupled with a first terminal of the capacitive device and a first terminal of the first transistor. The third end is coupled with a second terminal of the capacitive device and a first terminal of the second transistor. A second terminal of the first transistor and a second terminal of the second transistor are coupled together and are configured to receive a first control signal. A third terminal of the first transistor and a third terminal of the second transistor are coupled together and are configured to receive a second supply voltage different from the first supply voltage.

Abstract: A read time tracking mechanism (RTTM) for ensuring sufficient read time is provided. The read time tracking mechanism includes a read tracking circuit, which includes a tracking bit line (TBL) tracking circuit with one or more tracking cells, and a tracking word line (TWL). The RTTM also includes a sense amplifier enable (SAE) timing device configured to change the logic threshold of tracking WL (TWL) to delay the timing of signal change of TWL when necessary to ensure sufficient read time. The read time tracking mechanism is used to provide sufficient read time for memory arrays with various configurations, prepared under various process conditions, and operated under various voltages, and temperatures.

Abstract: Defect-describing (or “cut”) layer(s) for describing defects associated with different sides of a 3-dimensional (3D) structure enable fault modeling to determine the effect of position and location of defects on transistor performance. One or more defect-describing layers are used to identify the coordinates and sides of the 3D structures of the defects. The defect-describing layer(s) enables fault-modeling for 3D structures to understand the effects of faults on different locations, especially for defects associated with the fins of the finFET devices. Faults are injected to different locations and sides of fins and are modeled with different test vectors, test parameters and testing devices to identify detectable faults. The fault modeling would help identify the sources of defects and also improve layout design of finFET device structures.

Abstract: A current flowing through a voltage line and/or a data line in a column of a tracking circuit is determined. A threshold tracking time delay of the tracking circuit is determined. Based on the determined current handled by the voltage line and/or the data line and the determined threshold tracking time delay, a plurality of columns in the tracking circuit, a number of first cells in each column of the plurality of columns, and a number of second cells in the each column of the plurality of columns are determined.

Abstract: A circuit comprises a first set of first transistors and a second set of transistors. The first transistors are configured to be turned on in a sequential manner. The second transistors are configured to be turned on in a sequential manner after the first transistors are turned on. A transistor of the first set of first transistors corresponds to a first time delay. The first set of first transistors corresponds to a second time delay that is a multiple of the first time delay.

Abstract: A data split between a first data line and a second data line is caused to develop. At least one of the following sets of steps is performed: 1) a first power supply line of a sense amplifier is caused to rise towards a first power supply voltage value, and when the first power supply line reaches a first predetermined voltage value, the first power supply is caused to rise above the first power supply voltage value; and 2) a second power supply line of the sense amplifier is caused to fall towards a second power supply voltage value, and when the second power supply line reaches a second predetermined voltage value, the second power supply line is caused to fall below the second power supply voltage value.

Abstract: A sense amplifier includes a first transistor. The first transistor includes a gate connected to a bit line, and a first source/drain (S/D) electrically coupled with a global bit line. The sense amplifier further includes a second transistor. The second transistor includes a gate connected to a first signal line, and a first S/D coupled to the global bit line, wherein the second transistor is configured to pre-charge the bit line.