Abstract: A line driver with programmable slew rates is disclosed. The line driver can be configured to have a slew rate based on a desired fraction of the clock period of the system clock. Specifically, the clock period of the system clock signal is equal to a clock period reference number multiplied by a base delay. A number of base delays is calculated to be equal to the desired fraction of the clock period multiplied by the clock period reference number. The slew rate of the line driver is adjusted to be equal to the number of base delays.

Abstract: A system and method are provided for replacing dedicated external termination resistors typically used to implement an asymmetrical unidirectional bus I/O standard with programmable resistances that are dynamically selected by programming output driver circuits having digitally controlled impedances.

Abstract: A hot swap protection circuit (40) for an integrated circuit being plugged into a powered-up system includes a first circuit (10) for detecting a hot swap condition, a second circuit (20) coupled to the first circuit for preventing a pn junction diode (52) in a pull-up transistor (32) from going into a forward bias condition, and a third circuit (30) coupled to the first and second circuits for preventing the pull-up transistor from turning on during the hot swap condition.

Abstract: A system and method are provided for replacing dedicated external termination resistors typically used to implement an asymmetrical unidirectional bus I/O standard with programmable resistances that are dynamically selected by programming output driver circuits having digitally controlled impedances.

Abstract: A transmit variable-width interface can be programmed to convert an electronic digital data path that is either 1N, 2N, 4N, or 8N bits wide into a data path that is 2N bits wide, either by serializing bits (4N- or 8N-bit cases), re-clocking bits (2N-bit case), or grouping bits (1N-bit case). A receive variable-width interface can be programmed to convert a data path 2N bits wide into a data path that is 1N, 2N, 4N, or 8N bits wide. The widths of the two variable-width data paths are controlled independently. The variable-width interfaces are coupled between a multi-gigabit transceiver and core logic of a programmable logic device. The incoming and outgoing data paths of the variable-width interfaces have separate clocks signals that are synchronized such that small amounts of skew in these clock signals do not disrupt the operation of the variable-width interfaces.

Abstract: Described are systems for producing differential logic signals and circuits for biasing the voltages of the differential logic signals. These systems can be adapted for use with different loads by programming one or more programmable elements. One embodiment includes a series of driver stages, the outputs of which are connected to one another. The driver stages turn on successively to provide increasingly powerful differential amplification. This progressive increase in amplification produces a corresponding progressive decrease in output resistance, which reduces the noise associated with signal reflection. The systems can be incorporated into programmable IOBs to enable PLDs to provide differential output signals.

Abstract: A configuration memory architecture for an FPGA eliminates the need for a regular array of word lines and bit lines. The memory includes memory bytes, each of which has eight SRAM latches, a single flip-flop and a one-of-eight decoder having data input coupled to the inverting output of the flip-flop and eight individual data outputs, each of which is coupled to a data input of one of the SRAM latches. The flip-flops of all memory bytes for a logic block are coupled together in a serpentine shift register. Loading of configuration data involves shutting down all paths through the decoder, shifting all configuration bits for the “0” position SRAM latch of each memory byte into the shift register, and setting the address bits to the decoder so as to create a conductive path on each memory byte from the output of the flip-flop to the data input of the 0 latch. The process is then repeated for the seven other SRAM latch positions.

Abstract: Described are systems for producing differential logic signals and circuits for biasing the voltages of the differential logic signals. These systems can be adapted for use with different loads by programming one or more programmable elements. One embodiment includes a series of driver stages, the outputs of which are connected to one another. The driver stages turn on successively to provide increasingly powerful differential amplification. This progressive increase in amplification produces a corresponding progressive decrease in output resistance, which reduces the noise associated with signal reflection. The systems can be incorporated into programmable IOBs to enable PLDs to provide differential output signals.

Abstract: Described are systems for producing differential logic signals. These systems can be adapted for use with different loads by programming one or more programmable elements. One embodiment includes a series of driver stages, the outputs of which are connected to one another. The driver stages turn on successively to provide increasingly powerful differential amplification. This progressive increase in amplification produces a corresponding progressive decrease in output resistance, which reduces the noise associated with signal reflection. The systems can be incorporated into programmable IOBs to enable PLDs to provide differential output signals.

Abstract: A configuration memory architecture for an FPGA that eliminates the need for a regular array of word lines and bit lines is disclosed. The memory is comprised, in the preferred embodiment, of a plurality of memory bytes. Each memory byte has eight SRAM latches, a single flip flop and a one-of-eight decoder having a data input coupled to the inverting output of the flip flop and eight individual data outputs, each of which is coupled to a data input of one of the SRAM latches. The decoder also has address and write control inputs which are coupled to a state machine or other programmable device that controls the sequencing of the loading operation to load configuration data into the memory. The flip flops of all the memory bytes are coupled together in a serpentine shift register.

Abstract: A programmable input/output structure comprised of three input circuits and one output circuit coupled to the pin of an FPGA with the input circuits and output circuits being selectively enabled by programming bits so that input signals may be accepted from TTL, GTL, GTLP, LVPECL or LVDS type external circuits. The programming bits can also selectively enable an output driver to simultaneously drive the same pin of the FPGA as an output with signals which are either TTL or GTL or GTLP compatible. Further, the slew rate of the output driver is programmable between slow, medium or fast.

Abstract: A circuit and method for FPGAs to allow a user to supply a shutdown signal at an external pin which causes internal circuitry in the FPGA to turn off pass transistors in the word lines of every SRAM cell in the FPGA thereby preventing wasted power by current drain to ground through an SRAM cell that happens to be addressed when the FPGA is not being used.

Abstract: The present invention includes a central processing unit (CPU) coupled to a bus. Cache memory devices are coupled to the bus to receive memory requests from the CPU. Each of the cache memory devices includes a cache memory which is coupled to the controller circuit. The controller circuit provides control signals, which enable the cache memory to execute a memory operation requested by the CPU. The controller circuit is coupled to receive predefined address bits comprising memory addresses and memory requests issued by the CPU. Each of the controller circuits disposed in each cache memory device is further coupled to receive an identification number unique to each of the cache memory devices coupled to the bus.

Abstract: A duty cycle controller for generating proper control signals for an SRAM in an FPGA in the proper sequence and spaced at the proper times to guarantee proper operation of the SRAM regardless of the frequency of duty cycle of the clock selected by the user to synchronize and drive operations of the SRAM.

Abstract: A configurable SRAM for a field programmable gate array. Two memory arrays each have a data input, a data output, a write enable input and port A and B address inputs. First and second address buses are selectively coupled to the port A and port B address inputs through multiplexers such that different configurations can be achieved. The multiplexers are controlled by a dual port/single port steering signal and a x1/x2 steering signal such that the following configurations can be achieved: 32 x1 dual port; 32 x1 single port and 16 x2 single port. In dual port configurations, simultaneous read and write operations to different cells can occur. In x2 configuration, each array is operated as an independent memory with its own address input, its own data output and its own data input.

Abstract: An internal clock that generates a signal from a system clock is provided. The signal generated by the internal clock has a duty cycle that is independent of the system clock. The internal clock may be tuned to provide a desired duty cycle that corresponds to the period required for an operation such as a write to memory. The internal clock may provide a duty cycle that is longer or shorter than the system clock. The signal generated by the internal clock has the same period as the signal generated by the system clock to maintain synchronization of system operations.

Abstract: The architecture of the cache memory of the present invention includes a data RAM, a TAG RAM, a controller and pad logic on a single integrated circuit chip. The cache memory is coupled to a CPU and a memory bus controller over a host bus. The host bus receives read data from the cache memory and provides write data to the cache memory. The cache memory controller provides signals to the memory bus controller to indicate whether data accessed by the CPU resides in the cache memory. The present invention increases memory speed by allowing circuit elements in the cache memory to operate during both phases of a system clock signal.

Abstract: The method and apparatus of the present invention provides an interface between a testing device and a random access memory (RAM). The RAM comprises two types of RAM, a TAG RAM and a data RAM. In normal operation, the TAG RAM is not coupled to any devices external to the RAM. Thus, to test the TAG RAM, means must be provided to couple the testing device with the RAG RAM. One possible configuration for interface the TAG RAM with the testing device is to dedicate a line from the testing device to the TAG RAM for each output pin of the testing device, which significantly increases the size of the chip. To reduce this increase in size, according to the present invention, the write lines from the testing device share the bus used by the TAG RAM during normal operation. A multiplexer selects between the testing data and normal address data to insure the integrity of data over the bus.

Abstract: The charge shared precharge circuit of the present invention is coupled to the match line. The precharge circuit is disposed between the match line and a match line, and includes a CMOS passgate having an N channel and a P channel gate. An inverter acts as a match driver and is coupled between the match and match lines at the CMOS passgate's input and output. The input to the N channel gate of the pass gate is coupled through an inverter to the input of the P channel gate. The N channel gate is further coupled to V.sub.cc through two serially coupled P channel transistors receive BEQ line and an SAE signal, respectively. At the beginning of a compare cycle, BEQ is driven low as is SAE, thereby turning on the serially coupled P channel transistors and coupling V.sub.cc to the input of the N channel gate of the passgate. The P channel gate of the passgate is also opened due to the placement of the inverter between the N and P channel gates.

Abstract: The present invention discloses apparatus and methods for comparing the contents of two digital words and determining whether or not they identically match. The present invention's high speed compare circuit includes a plurality of bit compare block circuits (0 through N) which are coupled in a wired OR configuration to a match line. Each of the bit compare blocks receives a single bit from a first word A to be compared to a corresponding bit in a second word B. A charge share precharge circuit is coupled to the match line for precharging the match line to a voltage level of V.sub.cc /2. A match feed back circuit is also coupled to the match line and the charge precharge circuit to improve the speed at which the match line is precharged to the voltage level of V.sub.cc /2. A latch is coupled to the match line to electrically latch the state of the match line subsequent to the comparison operation.