Abstract: The present invention provides methods and apparatus for resetting all of the cells in a random access memory (RAM) during one clock cycle without requiring ancillary drivers. At the start of the reset cycle, each column in the memory array is selected to receive the reset value and then each data line in the array is driven low while the inverse of the data line is driven high. After a first predetermined delay, each word line is driven high and all of the memory cells are thus reset. The word lines are then driven low and after a second predetermined delay, the data lines are driven back to a high value. In this manner, each cell in the memory array is reset during one clock cycle.

Abstract: A high speed compare circuit includes a plurality of bit compare block circuits (0 through N) which are coupled in a wired OR configuration to a match line. Each bit compare block (0 through N) includes a compare circuit for receiving a bit and its complement from word A and a corresponding bit and its complement from word B. The compare circuit includes an output line which is normally maintained high to indicate that a match exists. The output line is coupled to a common mode dip filter which is comprised of N and P channel transistors. The output line of the compare circuit is coupled to the gates of a first and a second P channel transistor. The first P channel transistor is coupled to V.sub.cc, and the second P channel transistor is coupled in series to the first P channel transistor. The output line from the compare circuit is also coupled to the gate of an N channel transistor coupled in series with the first and second P channel transistors. The N channel transistor is also coupled to ground.