Patents by Inventor Audel A. Sanchez

Audel A. Sanchez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10141227
    Abstract: Methods and systems for achieving semiconductor-based circuits or systems having multiple components with one or more matched or similar characteristics or features are disclosed herein. In one example embodiment, a system includes a processing device that includes first, second, and third circuitry. The first circuitry is configured to generate control signals that at least indirectly cause a pick and place head mechanism to attempt to pick up and place at least some of first and second dice. The second circuitry is configured to assess whether attempts to implement one or more of first and second dice should be skipped based upon wafer map information. Further, the third circuitry is configured to determine whether a second position of a first one of the second dice is sufficiently proximate to a first position so that it would be appropriate to implement the first one of the second dice.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: November 27, 2018
    Assignee: NXP USA, INC.
    Inventors: Jose Luis Suarez, Gabriela Michel Sanchez, Audel Sanchez, Michele Lynn Miera, Flavio Hernandez Rodriguez
  • Publication number: 20180270960
    Abstract: An embodiment of an electronic device includes a circuit component (e.g., a transistor or other component) coupled to the top surface of a substrate. Encapsulation is formed over the substrate and the component. An opening in the encapsulation extends from the encapsulation top surface to a conductive feature on the top surface of the component. A conductive termination structure within the encapsulation opening extends from the conductive feature to the encapsulation top surface. The device also may include a second circuit physically coupled to the encapsulation top surface and electrically coupled to the component through the conductive termination structure. In an alternate embodiment, the conductive termination structure may be located in a trench in the encapsulation that extends between two circuits that are embedded within the encapsulation, where the conductive termination structure is configured to reduce electromagnetic coupling between the two circuits during device operation.
    Type: Application
    Filed: May 24, 2018
    Publication date: September 20, 2018
    Inventors: Lakshminarayan VISWANATHAN, Audel A. SANCHEZ, Fernando A. SANTOS, Jerry L. WHITE
  • Patent number: 9986646
    Abstract: An embodiment of an electronic device includes a circuit component (e.g., a transistor or other component) coupled to the top surface of a substrate. Encapsulation is formed over the substrate and the component. An opening in the encapsulation extends from the encapsulation top surface to a conductive feature on the top surface of the component. A conductive termination structure within the encapsulation opening extends from the conductive feature to the encapsulation top surface. The device also may include a second circuit physically coupled to the encapsulation top surface and electrically coupled to the component through the conductive termination structure. In an alternate embodiment, the conductive termination structure may be located in a trench in the encapsulation that extends between two circuits that are embedded within the encapsulation, where the conductive termination structure is configured to reduce electromagnetic coupling between the two circuits during device operation.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: May 29, 2018
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Audel A. Sanchez, Fernando A. Santos, Jerry L. White
  • Patent number: 9800208
    Abstract: An embodiment of a radio-frequency (RF) device includes at least one transistor, a package, and a surface-mountable capacitor. The package contains the at least one transistor and includes at least one termination. The surface-mountable capacitor is coupled in a shunt configuration between the at least one transistor and a power supply terminal of the device to decouple the at least one transistor from a power supply.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: October 24, 2017
    Assignee: NXP USA, INC.
    Inventors: Mahesh K. Shah, Jerry L. White, Li Li, Hussain H. Ladhani, Audel A. Sanchez, Lakshminarayan Viswanathan, Fernando A. Santos
  • Patent number: 9646897
    Abstract: The embodiments described herein provide a die crack detector and method that use a conductive trace arranged to at least substantially extend around a perimeter of an integrated circuit die. A one-time programmable element, such as a fuse, is coupled in series with the conductive trace, and a package lead is electrically coupled to both the fuse and another operational element on the integrated circuit die. With the fuse intact the package lead can thus be used to determine a measurement of the conductivity of the conductive trace, with the measurement of conductivity indicative of the presence of a crack on the die. After such testing the fuse can be electrically opened, and the package lead used for normal operation of the device on the packaged die without the conductive trace interfering with this operation.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: May 9, 2017
    Assignee: NXP USA, INC.
    Inventors: Audel A. Sanchez, Michele L. Miera, Robert A. Pryor, Jose L. Suarez
  • Patent number: 9466588
    Abstract: A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally conductive material. A die is mounted to a surface of the die carrier with die attach material having a melting point in excess of 240° C. A method may include providing the die carrier, melting the die attach material at a temperature in excess of 240° C. to attach the die to the surface of the die carrier to form a sub-assembly, attaching the sub-assembly to a leadframe, electrically interconnecting the die and the leadframe, and enclosing at least portions of the die and the leadframe to form a packaged device.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: October 11, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Fernando A. Santos, Audel A. Sanchez, Lakshminarayan Viswanathan
  • Publication number: 20160164471
    Abstract: An embodiment of a radio-frequency (RF) device includes at least one transistor, a package, and a surface-mountable capacitor. The package contains the at least one transistor and includes at least one termination. The surface-mountable capacitor is coupled in a shunt configuration between the at least one transistor and a power supply terminal of the device to decouple the at least one transistor from a power supply.
    Type: Application
    Filed: February 16, 2016
    Publication date: June 9, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Mahesh K. SHAH, Jerry L. WHITE, Li LI, Hussain H. LADHANI, Audel A. SANCHEZ, Lakshminarayan VISWANATHAN, Fernando A. SANTOS
  • Publication number: 20160163623
    Abstract: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.
    Type: Application
    Filed: February 11, 2016
    Publication date: June 9, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Lakshminarayan Viswanathan, Lakshmi N. Ramanathan, Audel A. Sanchez, Fernando A. Santos
  • Publication number: 20160150632
    Abstract: An embodiment of an electronic device includes a circuit component (e.g., a transistor or other component) coupled to the top surface of a substrate. Encapsulation is formed over the substrate and the component. An opening in the encapsulation extends from the encapsulation top surface to a conductive feature on the top surface of the component. A conductive termination structure within the encapsulation opening extends from the conductive feature to the encapsulation top surface. The device also may include a second circuit physically coupled to the encapsulation top surface and electrically coupled to the component through the conductive termination structure. In an alternate embodiment, the conductive termination structure may be located in a trench in the encapsulation that extends between two circuits that are embedded within the encapsulation, where the conductive termination structure is configured to reduce electromagnetic coupling between the two circuits during device operation.
    Type: Application
    Filed: November 21, 2014
    Publication date: May 26, 2016
    Inventors: LAKSHMINARAYAN VISWANATHAN, AUDEL A. SANCHEZ, FERNANDO A. SANTOS, JERRY L. WHITE
  • Patent number: 9300254
    Abstract: An embodiment of a radio-frequency (RF) device includes at least one transistor, a package, and a surface-mountable capacitor. The package contains the at least one transistor and includes at least one termination. The surface-mountable capacitor is coupled in a shunt configuration between the at least one transistor and a power supply terminal of the device to decouple the at least one transistor from a power supply.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: March 29, 2016
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventors: Mahesh K. Shah, Jerry L. White, Li Li, Hussain H. Ladhani, Audel A. Sanchez, Lakshminarayan Viswanathan, Fernando A. Santos
  • Patent number: 9263375
    Abstract: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: February 16, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Lakshminarayan Viswanathan, Lakshmi N. Ramanathan, Audel A. Sanchez, Fernando A. Santos
  • Publication number: 20150381117
    Abstract: An embodiment of a radio-frequency (RF) device includes at least one transistor, a package, and a surface-mountable capacitor. The package contains the at least one transistor and includes at least one termination. The surface-mountable capacitor is coupled in a shunt configuration between the at least one transistor and a power supply terminal of the device to decouple the at least one transistor from a power supply.
    Type: Application
    Filed: June 26, 2014
    Publication date: December 31, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Mahesh K. SHAH, Jerry L. WHITE, Li LI, Hussain H. LADHANI, Audel A. SANCHEZ, Lakshminarayan VISWANATHAN, Fernando A. SANTOS
  • Patent number: 9196520
    Abstract: Systems and methods for releasing semiconductor dies from an adhesive tape or film. In some embodiments, a semiconductor manufacturing device may include: a chuck plate configured to support an array of semiconductor dies, where each die in the array has a top surface and a bottom surface, where each die's bottom surface is bonded to an adhesive tape, and where the chuck plate comprises one or more channels configured to apply a negative pressure to the adhesive tape; and a tape release element having an irregular surface, the tape release element disposed between the chuck plate and the adhesive tape.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: November 24, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Audel A. Sanchez, Michael L. Eleff, Jose L. Suarez
  • Patent number: 9159588
    Abstract: A method for a packaged leadless semiconductor device including a heat sink flange to which semiconductor dies are coupled using a high temperature die attach process. The semiconductor device further includes a frame structure pre-formed with bent terminal pads. The frame structure is combined with the flange so that a lower surface of the flange and a lower section of each terminal pad are in coplanar alignment, and so that an upper section of each terminal pad overlies the flange. Interconnects interconnect the die with the upper section of the terminal pad. An encapsulant encases the frame structure, flange, die, and interconnects with the lower section of each terminal pad and the lower surface of the flange remaining exposed from the encapsulant.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: October 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Audel A. Sanchez, Fernando A. Santos, Lakshminarayan Viswanathan
  • Publication number: 20150249021
    Abstract: A method for a packaged leadless semiconductor device including a heat sink flange to which semiconductor dies are coupled using a high temperature die attach process. The semiconductor device further includes a frame structure pre-formed with bent terminal pads. The frame structure is combined with the flange so that a lower surface of the flange and a lower section of each terminal pad are in coplanar alignment, and so that an upper section of each terminal pad overlies the flange. Interconnects interconnect the die with the upper section of the terminal pad. An encapsulant encases the frame structure, flange, die, and interconnects with the lower section of each terminal pad and the lower surface of the flange remaining exposed from the encapsulant.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 3, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Audel A. Sanchez, Fernando A. Santos, Lakshminarayan Viswanathan
  • Patent number: 9111901
    Abstract: Embodiments of methods for forming a semiconductor device that includes a die and a substrate include pressing together the die and the substrate such that a first gold layer and one or more additional material layers are between the die and the substrate, and performing a bonding operation to form a die attach layer between the die and the substrate. The die attach layer includes a gold interface layer that includes gold and a plurality of first precipitates in the gold. Each of the first precipitates includes a combination of nickel, cobalt, palladium, gold, and silicon.
    Type: Grant
    Filed: May 26, 2014
    Date of Patent: August 18, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jin-Wook Jang, Lalgudi M. Mahalingam, Audel A. Sanchez, Lakshminarayan Viswanathan
  • Patent number: 9111984
    Abstract: The embodiments described herein provide an apparatus and method for separating dies from adhesive tape. In general, these techniques use applied vacuum and one or more channels in an extractor base surface to progressively peel adhesive tape away from the die. When the adhesive tape has been peeled away from the entire die the die can be removed and packaged. Such a technique can reduce the strain the die and thus may reduce the probability of cracks occurring in the die, and is thus particularly applicable to removing adhesive tape from relatively thin dies.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: August 18, 2015
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventors: Audel A. Sanchez, David F. Abdo, Michael L. Eleff
  • Patent number: 9105599
    Abstract: Embodiments of a semiconductor device include a primary portion of a substrate, a die, and a die attach layer between the die and the primary portion of the substrate. The die attach layer includes a gold interface layer that includes gold and a plurality of first precipitates in the gold. Each of the first precipitates includes a combination of nickel, cobalt, palladium, gold, and silicon.
    Type: Grant
    Filed: May 26, 2014
    Date of Patent: August 11, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jin-Wook Jang, Lalgudi M. Mahalingam, Audel A. Sanchez, Lakshminarayan Viswanathan
  • Publication number: 20150171057
    Abstract: A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally conductive material. A die is mounted to a surface of the die carrier with die attach material having a melting point in excess of 240° C. A method may include providing the die carrier, melting the die attach material at a temperature in excess of 240° C. to attach the die to the surface of the die carrier to form a sub-assembly, attaching the sub-assembly to a leadframe, electrically interconnecting the die and the leadframe, and enclosing at least portions of the die and the leadframe to form a packaged device.
    Type: Application
    Filed: February 23, 2015
    Publication date: June 18, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: FERNANDO A. SANTOS, AUDEL A. SANCHEZ, LAKSHMINARAYAN VISWANATHAN
  • Publication number: 20150115266
    Abstract: The embodiments described herein provide a die crack detector and method that use a conductive trace arranged to at least substantially extend around a perimeter of an integrated circuit die. A one-time programmable element, such as a fuse, is coupled in series with the conductive trace, and a package lead is electrically coupled to both the fuse and another operational element on the integrated circuit die. With the fuse intact the package lead can thus be used to determine a measurement of the conductivity of the conductive trace, with the measurement of conductivity indicative of the presence of a crack on the die. After such testing the fuse can be electrically opened, and the package lead used for normal operation of the device on the packaged die without the conductive trace interfering with this operation.
    Type: Application
    Filed: October 28, 2013
    Publication date: April 30, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Audel A. SANCHEZ, Michele L. MIERA, Robert A. PRYOR, Jose L. SUAREZ