Abstract: A Josephson junction (JJ) device is disclosed that includes a first superconductor structure having a bottom superconductor arm portion and a second superconductor structure having a top superconductor arm portion disposed substantially orthogonal to the bottom superconductor arm portion and overlapping the bottom superconductor arm portion in a JJ operation region. The JJ device further includes a dielectric material layer acting as a tunnel barrier disposed between the bottom superconductor arm portion and the top superconductor arm portion in the JJ operation region to form an operating JJ.

Abstract: A superconductor system is provided that includes a superconductor device comprising a plurality of superconductor layers and dielectric layers interleaved with the plurality of superconductor layers, wherein at least one superconductor layer is a ground plane. The superconductor device further includes superconductor circuitry that resides within one or more of the plurality of superconductor layers, and one or more active moats extending through the plurality of superconductor layers and the dielectric layers, wherein at least one flux vortex caused by cryogenic cooling can be removed from at least one of the plurality of superconductor layers into the one or more active moats by the activating and deactivating of the one or more active moats.

Abstract: A superconducting DC switch system is provided. The superconducting DC switch system comprises one or more Josephson junctions (JJs), and a magnetic field generator that is configured to switch from inducing a magnetic field in a plane of the one or more JJs, and providing no magnetic field in the plane of the one or more JJs. A DC input signal applied at an input of the one or more JJs is passed through to an output the one or more JJs in the absence of an induced magnetic field, and the DC input signal is substantially suppressed at the output of the one or more JJs in the presence of the magnetic field.

Abstract: A superconducting AC switch system includes a switch network configuration comprising a Josephson junction (JJ) coupled to a transmission line having a transmission line impedance, and a magnetic field generator that is configured to switch from inducing a magnetic field in a plane of the JJ, and providing no magnetic field in the plane of the JJ. An AC input signal applied at an input of the switch network configuration is passed through to an output of the switch network configuration in a first magnetic state, and substantially reflected back to the input of the switch network configuration in a second magnetic state. The first magnetic state is one of inducing and not inducing a magnetic field in a plane of the JJ, and the second magnetic state is the other of inducing and not inducing a magnetic field in a plane of the JJ.

Abstract: A superconducting DC switch system is provided. The superconducting DC switch system comprises one or more Josephson junctions (JJs), and a magnetic field generator that is configured to switch from inducing a magnetic field in a plane of the one or more JJs, and providing no magnetic field in the plane of the one or more JJs. A DC input signal applied at an input of the one or more JJs is passed through to an output the one or more JJs in the absence of an induced magnetic field, and the DC input signal is substantially suppressed at the output of the one or more JJs in the presence of the magnetic field.

Abstract: Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

Abstract: A superconducting AC switch system includes a switch network configuration comprising a Josephson junction (JJ) coupled to a transmission line having a transmission line impedance, and a magnetic field generator that is configured to switch from inducing a magnetic field in a plane of the JJ, and providing no magnetic field in the plane of the JJ. An AC input signal applied at an input of the switch network configuration is passed through to an output of the switch network configuration in a first magnetic state, and substantially reflected back to the input of the switch network configuration in a second magnetic state. The first magnetic state is one of inducing and not inducing a magnetic field in a plane of the JJ, and the second magnetic state is the other of inducing and not inducing a magnetic field in a plane of the JJ.

Abstract: A method of forming a superconductor structure is disclosed. The method comprises forming a superconductor line in a first dielectric layer, forming a resistor with an end coupled to an end of the superconductor line, and forming a second dielectric layer overlying the resistor. The method further comprises etching a tapered opening through the second dielectric layer to the resistor, and performing a contact material fill with a normal metal material to fill the tapered opening and form a normal metal connector coupled to the resistor.

Abstract: Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

Abstract: A method of forming a superconductor structure is disclosed. The method comprises forming a superconductor line in a first dielectric layer, forming a resistor with an end coupled to an end of the superconductor line, and forming a second dielectric layer overlying the resistor. The method further comprises etching a tapered opening through the second dielectric layer to the resistor, and performing a contact material fill with a normal metal material to fill the tapered opening and form a normal metal connector coupled to the resistor.

Abstract: Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

Abstract: A system for measuring critical temperatures of superconducting components of a superconducting circuit housed in a cryogenic chamber with a controllable ambient temperature is described. The superconducting circuit can have a plurality of superconductor-resistor pairs connected in series. Each of the plurality of superconductor-resistor pairs can include a superconducting component and a resistor coupled in parallel with the superconducting component. The system can also include a resistance meter that measures a resistance of the superconducting circuit. The system further includes a controller that commands the cryogenic chamber to gradually sweep the ambient temperature. The controller can also record an instant ambient temperature as a critical temperature for a given superconducting component of a corresponding one of the plurality of superconductor-resistor pairs in response to detecting a change in a measured resistance across an input node and an output node of the superconducting circuit.

Abstract: Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

Abstract: A system for measuring critical temperatures of superconducting components of a superconducting circuit housed in a cryogenic chamber with a controllable ambient temperature is described. The superconducting circuit can have a plurality of superconductor-resistor pairs connected in series. Each of the plurality of superconductor-resistor pairs can include a superconducting component and a resistor coupled in parallel with the superconducting component. The system can also include a resistance meter that measures a resistance of the superconducting circuit. The system further includes a controller that commands the cryogenic chamber to gradually sweep the ambient temperature. The controller can also record an instant ambient temperature as a critical temperature for a given superconducting component of a corresponding one of the plurality of superconductor-resistor pairs in response to detecting a change in a measured resistance across an input node and an output node of the superconducting circuit.

Abstract: A method is provided of forming a superconductor device interconnect structure. The method includes forming a first high temperature dielectric layer overlying a substrate, forming a base electrode in the first high temperature dielectric layer with the base electrode having a top surface aligned with the top surface of the first high temperature dielectric layer, and depositing a second high temperature dielectric layer over the first high temperature dielectric layer and the base electrode. The method further comprises forming a first contact through the second dielectric layer to a first end of the base electrode, forming a Josephson junction (JJ) overlying and in contact with the first contact, and forming a second contact through the second dielectric layer to a second end of the base electrode.

Abstract: A method is provided of forming a superconductor device interconnect structure. The method includes forming a first high temperature dielectric layer overlying a substrate, forming a base electrode in the first high temperature dielectric layer with the base electrode having a top surface aligned with the top surface of the first high temperature dielectric layer, and depositing a second high temperature dielectric layer over the first high temperature dielectric layer and the base electrode. The method further comprises forming a first contact through the second dielectric layer to a first end of the base electrode, forming a Josephson junction (JJ) overlying and in contact with the first contact, and forming a second contact through the second dielectric layer to a second end of the base electrode.

Abstract: A method is provided of forming a superconductor device interconnect structure. The method includes forming a first high temperature dielectric layer overlying a substrate, forming a base electrode in the first high temperature dielectric layer with the base electrode having a top surface aligned with the top surface of the first high temperature dielectric layer, and depositing a second high temperature dielectric layer over the first high temperature dielectric layer and the base electrode. The method further comprises forming a first contact through the second dielectric layer to a first end of the base electrode, forming a Josephson junction (JJ) overlying and in contact with the first contact, and forming a second contact through the second dielectric layer to a second end of the base electrode.

Abstract: A method is provided of forming a superconductor device interconnect structure. The method includes forming a first high temperature dielectric layer overlying a substrate, forming a base electrode in the first high temperature dielectric layer with the base electrode having a top surface aligned with the top surface of the first high temperature dielectric layer, and depositing a second high temperature dielectric layer over the first high temperature dielectric layer and the base electrode. The method further comprises forming a first contact through the second dielectric layer to a first end of the base electrode, forming a Josephson junction (JJ) overlying and in contact with the first contact, and forming a second contact through the second dielectric layer to a second end of the base electrode.

Abstract: Methods and systems for semiconductor line scribe centering are provided. A method includes placing and measuring substantially identical test macros within a chip and in a scribe line. The method also includes establishing an estimate correlation between scribe line measurements taken during a manufacturing process and product measurements taken on a final product. The method also includes determining empirical scribe line specification limits consistent with established product screen limits. The method also includes adjusting the manufacturing process in order to optimize performance to the empirical scribe line specification limits.

Abstract: Embodiments of the present invention disclose an apparatus and method to determine the intra-chip variation of an integrated circuit. In an embodiment, an apparatus comprises a test macro that includes two or more test structures; wherein each test structure includes identical copies of the same performance monitor; wherein each performance monitor has a unique bounding circuitry that encompasses the performance monitor; and wherein the two or more test structures are positioned close enough to each other as to reduce systematic across chip variation between the two or more test structures.