Abstract: Embodiments of the present invention disclose an apparatus and method to determine the intra-chip variation of an integrated circuit. In an embodiment, an apparatus comprises a test macro that includes two or more test structures; wherein each test structure includes identical copies of the same performance monitor; wherein each performance monitor has a unique bounding circuitry that encompasses the performance monitor; and wherein the two or more test structures are positioned close enough to each other as to reduce systematic across chip variation between the two or more test structures.

Abstract: A computer determines a component optimal yield point for each component of the plurality of components, where the component optimal yield point represents the process parameter values where maximum yield is achieved for a component. The computer determines a weight factor for each component of the plurality of components, where the weight factor represents an importance of a component to the semiconductor device. The computer then determines an overall optimal yield point based on the component yield point and weight factor determined for each component of the plurality of components, the overall optimal yield point representing the process parameter values where maximum yield is achieved for the semiconductor device.

Abstract: Methods and systems for semiconductor line scribe centering are provided. A method includes placing and measuring substantially identical test macros within a chip and in a scribe line. The method also includes establishing an estimate correlation between scribe line measurements taken during a manufacturing process and product measurements taken on a final product. The method also includes determining empirical scribe line specification limits consistent with established product screen limits. The method also includes adjusting the manufacturing process in order to optimize performance to the empirical scribe line specification limits.