Abstract: A field programmable gate array (FPGA) device includes a high-speed serializer/deserializer (SERDES). The field programmable gate array allows programmable built-in testing of the SERDES at operating speeds. A digital clock manager circuit allows clock signals coupled to the SERDES to be modified during the test operations to stress the SERDES circuit. The logic array of the FPGA can be programmed to generate test patterns and to analyze data received by the SERDES circuit. Cyclic redundancy check (CRC) characters, or other error checking characters, can also be generated using the logic array. During testing, the FPGA can perform extensive tests on the communication circuitry and store the results of the testing. An external tester can read the results of the test without substantial test time or complicated test equipment. After testing is complete, the device may be re-programmed to perform the end-user function, adding zero cost to the device for test implementation.

Abstract: A communication device (50) operating at a plurality of frequencies has a processor (36) coupled to a semiconductor die integrated antenna structure (30) having a first integrated antenna (14) tuned to a first frequency and coupled to a first circuit (17) and at least a second integrated antenna (18) tuned to a second frequency and coupled to a second circuit (21). The processor controls either the first circuit or the second circuit or both.

Abstract: An FPGA has an on-chip processor that reads configuration data onto the FPGA and controls the loading of that configuration data into FPGA configuration memory cells. After FPGA power-up, the processor reads a configuration mode code from predetermined terminals of the FPGA. If the configuration mode code has a first value, then the processor executes a first configuration program so that configuration data is received onto the FPGA in accordance with a first configuration mode. If the configuration mode code has a second value, then the processor executes a second configuration program so that configuration data is received onto the FPGA in accordance with a second configuration mode. The configuration programs can be stored in metal-mask ROM on-chip so they can be changed without re-laying out the remainder of the FPGA. Providing multiple configuration programs allows the FPGA to support multiple configuration modes using the same processor hardware.

Abstract: The supply voltage to which a delay circuit's buffer stages are coupled is adjusted in response to changes in temperature according to a predetermined relationship to maintain a substantially constant buffer stage gate delay over temperature variations. Decreasing gate delays resulting from decreases in temperature are offset by decreasing the supply voltage, which in turn increases gate delays. Conversely, increasing gate delays resulting from increases in temperature are offset by increasing the supply voltage, which in turn decreases gate delays. In some embodiments, a control circuit is connected to the reference voltage circuit that supplies VCC to the delay circuit, and adjusts VCC in response to temperature to maintain substantially constant gate delay over temperature. In one embodiment, the control circuit includes a microprocessor and a look-up table containing desired supply voltage versus temperature mappings.

Abstract: A programmable logic device makes better use of its I/O terminals (for example, package pins) by both amplitude and phase encoding a stream of multi-bit digital values into a single DATA signal. Information in the DATA signal is encoded into four different voltage levels and four different phases. The DATA signal is communicated from the FPGA via just one I/O terminal, as opposed to many I/O terminals. An amplitude/phase encoder is described that includes a delay line in a delay-locked loop, as well as two other delay lines that are slaved to the delay line of the delay-locked loop. The slaved delay lines are used to phase encode the information into the DATA signal. An amplitude/phase decoder is also described that enables the programmable logic device to receive and decode such a DATA signal. The amplitude/phase decoder includes a delay line in a delay-locked loop, as well as two other delay lines that are slaved to the delay line of the delay-locked loop.

Abstract: Method and apparatus for preconditioning and in-use conditioning of transistors formed on a semiconductor-on-insulator structure is described. More particularly, transistors of a programmable logic device (PLD), such as a field programmable gate array (FPGA), are preconditioned to take advantage of charge accumulation owing to a “floating body” effect. This preconditioning takes a form of switching transistors on and off prior to customer operation. Accordingly, semiconductor-on-insulator transistors accumulate charge during this switching period, so when customer operation takes place, transistor switching times are less variable over a period of operation of the PLD. Additionally, a design process and implementation is described for identification and in-use conditioning of transistors that may need conditioning during customer operation to control switching time variability.

Abstract: A phase-locked loop (PLL) having a wide range of oscillator output frequencies and a wide range of loop divider values is realizable in integrated form because the total capacitance of its loop filter is small. The PLL includes a first phase detector, a second phase detector, a programmable tapped-delay-line oscillator, a divide-by-M loop divider, and a programmable on-chip loop filter. The programmable filter is programmed to realize one of many loop filters. In a first step, oscillator output is fed back via the loop divider to the first phase detector. Oscillator frequency is decremented by changing tap selection inside the oscillator until the first phase detector determines that the frequency of the signal fed back via the loop divider (divide-by-M) is smaller than the frequency of an input signal. The tap control at which this frequency lock condition occurred, along with value M, is then used to determine which of the many loop filters will be used in a phase lock step.

Abstract: A clock signal is monitored to detect a transition from a first logic state to a second logic state. Once this transition is detected, subsequent transitions of the clock signal are ignored for a predetermined time period during which signal interference is most significant. After lapse of the predetermined time period, the clock signal is again monitored to detect subsequent state transitions. In some embodiments, the clock signal is delayed using a delay circuit to produce a delayed clock signal which is used to force the clock signal to the second logic state for a predetermined time period. In one embodiment, the predetermined time period is user-selectable via one or more selectable taps on the delay circuit.

Abstract: An analog-to-digital converter (ADC) is realized in a field programmable gate array (FPGA) without adding special dedicated analog circuitry. In a digital application, a comparator in an interface cell of the FPGA compares an incoming digital signal to a reference voltage. Adjusting of the reference voltage allows the interface cell to support different digital I/O standards. In one embodiment, the comparator is not used for this digital purpose, but rather is used as a comparator in an ADC. A flash ADC is realized by using the comparators of numerous interface cells as the comparators of the flash ADC. Conversion speed is increased by reducing the impedance of the analog signal input path. An on-chip resistor string is provided so that the flash ADC can be realized without external components. In another embodiment, the comparator of the interface cell is the comparator of a successive approximation ADC.

Abstract: The maximum propagation speed of an electrical signal travelling on a conductor in an integrated circuit is limited by the dielectric constant of the dielectric material surrounding the conductor. Rather than transmitting an electrical signal through a conductor that is surrounded with a dielectric material having a dielectric constant of two or more, the signal is propagated as an electromagnetic wave through air at a much higher speed across the surface of the integrated circuit. In one embodiment, a radio frequency (RF) signal is passed into an integrated circuit package via a transmission line. The transmission line supplies the RF signal to a waveguide-like structure disposed above the integrated circuit inside the package. The RF signal propagates as an electromagnetic wave through air in the waveguide structure across the upper surface of the integrated circuit.

Abstract: The maximum propagation speed of an electrical signal travelling on a conductor in an integrated circuit is limited by the dielectric constant of the dielectric material surrounding the conductor. Rather than transmitting an electrical signal through a conductor that is surrounded with a dielectric material having a dielectric constant of two or more, the signal is propagated as an electromagnetic wave through air at a much higher speed across the surface of the integrated circuit. In one embodiment, a radio frequency (RF) signal is passed into an integrated circuit package via a transmission line. The transmission line supplies the RF signal to a waveguide-like structure disposed above the integrated circuit inside the package. The RF signal propagates as an electromagnetic wave through air in the waveguide structure across the upper surface of the integrated circuit.

Abstract: An analog-to-digital converter (ADC) is realized in a field programmable gate array (FPGA) without adding special dedicated analog circuitry. In a digital application, a comparator in an interface cell of the FPGA compares an incoming digital signal to a reference voltage. Adjusting of the reference voltage allows the interface cell to support different digital I/O standards. In one embodiment, the comparator is not used for this digital purpose, but rather is used as a comparator in an ADC. A flash ADC is realized by using the comparators of numerous interface cells as the comparators of the flash ADC. Conversion speed is increased by reducing the impedance of the analog signal input path. An on-chip resistor string is provided so that the flash ADC can be realized without external components. In another embodiment, the comparator of the interface cell is the comparator of a successive approximation ADC.

Abstract: A clock signal is driven at one point onto a clock bus of an integrated circuit by a driver circuit. Oscillators are coupled along the length of the clock bus. The oscillators are all loosely coupled to one another through the clock bus such that all the oscillators oscillate together at the frequency of the clock signal. The oscillators add energy to the clock signal on the clock bus locally so that all the energy required to sustain the clock signal does not have to come from the point of origin. By reducing current flow down the clock bus across the series resistance of the clock bus, limits on propagation speed due to the series resistance of the clock bus are avoided. In one embodiment, less than 15 milliwatts is consumed to “propagate” a 1.36 gigahertz clock signal a distance of two centimeters down a clock bus of an integrated circuit at a propagation speed of approximately 2.1×107 meters per second.

Abstract: The maximum propagation speed of an electrical signal travelling on a conductor in an integrated circuit is limited by the dielectric constant of the dielectric material surrounding the conductor. Rather than transmitting an electrical signal through a conductor that is surrounded with a dielectric material having a dielectric constant of two or more, the signal is propagated as an electromagnetic wave through air at a much higher speed across the surface of the integrated circuit. In one embodiment, a radio frequency (RF) signal is passed into an integrated circuit package via a transmission line. The transmission line supplies the RF signal to a waveguide-like structure disposed above the integrated circuit inside the package. The RF signal propagates as an electromagnetic wave through air in the waveguide structure across the upper surface of the integrated circuit.

Abstract: A digital locked loop which can act as a slave clock. The digital loop is able to monitor a master clock signal and adjust its own output to accurately track the frequency of the master clock signal. In addition, the digital loop can generate a highly accurate timing signal in the absence of the master clock. An oscillator supplies a signal having a fixed frequency to a digital synthesizer. The synthesizer treats the oscillator frequency as a known standard. The synthesizer uses that standard to generate an output signal with a different frequency. The frequency of the output signal is chosen so that it is equal to a frequency supplied by an external master clock. The present invention utilizes a digital feedback loop to detect any phase shift between the output signal and the master clock signal. The presence of any phase shift indicates that the frequency of the master clock signal has changed.

Abstract: A personal branch exchange telephone system including improved interface circuitry to couple the system to outside telephone lines as well as to individual telephone sets on extension lines in the PBX system. The PBX system is connected to the telephone lines only through electromagnetic coupling and circuitry is provided to detect both ringing signals and loop current carried by the telephone lines.

Abstract: A telephone call diverting and answering system. The system includes a telephone call concentrator for diverting a telephone call placed at a telephone set at one of a number of calling stations, from a telephone line connected to the intended telephone set, at one of a large number of called stations, to one of a small number of telephone trunks leading to sets at a number of answering stations. The system further includes an operator console at each answering station, and a traffic director for assigning the call to a particular station by causing the identity of the called station and the number of the diverting trunk to be displayed on the operator console of the assigned answering station.