Abstract: A memory cell stores a data bit value despite atomic radiation. The memory cell includes two inverters, an access circuit, and two switch circuits. Each inverter has an input and an output. The access circuit is arranged to write and read the data bit value in the memory cell. The switch circuits cross couple the outputs of the two inverters to the inputs of the two inverters. The switch circuits are arranged to alternately decouple and couple the inputs of the two inverters to limit corruption from atomic radiation of the data bit value in the memory cell.

Abstract: An integrated circuit fabricated in a multiple oxide process can be used to provide a temperature-insensitive circuit. The temperature-insensitive circuit can be a ring oscillator; this ring oscillator can be used as a low-cost integrated reference frequency to monitor and to modify the behavior of the integrated to produce the desired results. In some embodiments, the reference oscillator output can be compared to second oscillator output where the second oscillator performance is temperature-sensitive. The comparison result can be monitored and processed to power down the integrated circuit.

Abstract: A method of correcting errors stored in a memory array is disclosed. According to various embodiments of the invention, the method comprises the steps of storing data in the memory array; reading back the data stored in the memory array; performing a check for errors on each frame of data in a first direction; and performing a check for errors in a second direction. The step of performing a check for errors may include a parity check or a cyclical redundancy check. Depending upon the number of errors detected in intersecting rows and columns, the state of cells of the memory array are selectively changed.

Abstract: Prediction of a rate of atmospheric upsets in an integrated circuit (IC) is described. In one embodiment, a first rate of atmospheric upsets is measured in a plurality of ICs of a first type. Within a beam of atomic particles, a second rate of beam upsets of at least one IC of the first type and a third rate of beam upsets of at least one IC of a second type are concurrently measured. A fourth rate of atmospheric upsets is determined in an IC of the second type as a function of the first rate of atmospheric upsets and the second and third rates of beam upsets.

Abstract: A circuit for preventing an error in a flip-flop is disclosed. The circuit comprises an input circuit for receiving input data; a circuit for generating true and complement data associated with each of the input data and redundant data at predetermined nodes of the circuit; and a plurality of inverters each controlled by an associated node, wherein an inverter node of each inverter of the plurality of inverters is coupled to a separate node of the predetermined nodes. A method of preventing an error in a flip-flop is also disclosed.

Abstract: A low jitter digital frequency synthesizer includes a first counter module, a second counter module, a snapshot module, an error value generation module, and a tapped delay line. The first counter module counts intervals of M cycles of an input clock to produce a first count. The second counter module count intervals of D cycles of an output clock to produce a second count, wherein an average rate of the output clock corresponds to M/D times a rate of the input clock. The snapshot module periodically takes a snapshot of the first and second counts to produce snapshots. The error value generation module generates a modulated error value based on the snapshots and a modulation value, where the modulation value is used to spread the spectrum of the output clock. The tapped delay line module produces the output clock based on the modulated error value.

Abstract: SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.

Abstract: Method and apparatus for testing duty cycle at an input/output node is described. A test signal is generated having a non-zero frequency and a duty cycle. The test signal is sampled using a sampling signal. The phase of the sampling signal is shifted to detect a first level change in the sampled test signal. The phase of the sampling signal is then shifted to detect a second level change in the sampled test signal. The duty cycle of the test signal is computed using a phase indicator of the sampling signal at the first level change and a phase indicator of the sampling signal at the second level change.

Abstract: A circuit for implementing a plurality of circuits on a programmable logic device, the circuit comprising a first circuit implemented on a first portion of the programmable logic device; a second circuit implemented on a second portion of the programmable logic device; and a control circuit coupled to the first circuit and the second circuit, the control circuit providing isolation between the first circuit and the second circuit. While the first circuit and the second circuit may comprise redundant circuits implementing a common function, the circuits may also comprise circuits which must be isolated, such as an encryption circuit and a decryption circuit implementing a cryptographic function. A method for implementing a plurality of circuits on a programmable logic device is also disclosed.

Abstract: Determining voltage level validity for a power-on reset condition is described. A supply voltage is applied to an integrated circuit. An oscillating signal is generated responsive to the supply voltage applied. A counting occurs responsive to oscillations of the oscillating signal. A triggering occurs responsive to reaching a first voltage level of the supply voltage for the power-on reset condition. A first count of the counting occurs responsive to the triggering. A second count is selected responsive to the first count. A second level is accepted as having at least met a threshold for the supply voltage responsive to the counting reaching the second count for the power-on reset condition.

Abstract: In an integrated circuit, a layer including a plurality of conductive wires is described. A first wire, having sidewalls, is tapered from a proximal end which has a first width to a distal end which has a second width, to reduce width from the first width to the second width, and the first wire also has a substantially vertical surface. A second wire, spaced apart from the first wire, also has a substantially vertical surface. The first wire and the second wire are each horizontally disposed along side each other forming a part of a sidewall capacitor between facing sidewalls. Capacitors are created between the first substantially vertical surface and the second substantially vertical surface, the capacitors are respectively associated with capacitances and with a plurality of loads, the plurality of loads is progressively reduced responsive to a progressive reduction of the capacitances as associated with the first wire taper.

Abstract: A programmable logic device (PLD) includes a plurality of configurable resources, a programmable interconnect having a plurality of signal lines for providing a number of dedicated signal paths between any of the configurable resources, and a subway routing system having a shared subway bus coupled to the signal lines of the programmable interconnect at a plurality of connection points by a plurality of corresponding subway ports. The subway routing system, which provides alternate routing resources for the programmable interconnect, may be used to route different signals between different configurable resources at different times.

Abstract: A method of and apparatus for generating a spread spectrum clock signal on an integrated circuit are provided. A target frequency generated by a ring oscillator can be modulated by varying a supply voltage to the ring oscillator, thereby changing the target frequency. In one embodiment, the supply voltage is generated by an analog multiplexer that can be digitally controlled. A fixed voltage source can provide an input signal to the analog multiplexer. In one embodiment, the fixed voltage source can be implemented with a unity gain amplifier.

Abstract: A method of implementing a design on a programmable logic device (PLD) includes generating a database that identifies correspondence between resources and programming frames of the PLD. A first PLD design is compiled, wherein the first design uses a first set of resources in a first manner. Costs associated with using the first set of resources of the first design in the first manner are reduced. A second PLD design is then compiled, applying the reduced costs associated with using the first set of resources. A second set of resources required to compile the second design is identified, wherein the second set of resources is not used in the same manner as the first set of resources. A set of programming frames associated with the second set of resources is identified. Costs associated with using a third set of resources associated with the set of programming frames are increased.

Abstract: The performance of a serial data transceiver in a programmable logic device may be determined by applying a stress sequence of sequential data to a receiver of the transceiver, comparing the received data to reference data and determining the number of errors.

Abstract: A system and method are disclosed for error correction in a programmable logic device (PLD). A frame circuit retrieves data from each column of configuration memory of the PLD, and a check memory stores of a plurality of check words. A buffer circuit is coupled to the check memory and to the frame circuit. The buffer circuit assembles blocks of data from data retrieved by the frame circuit and from corresponding check words in the check memory. A plurality of storage elements are provided for storage of status information. A check circuit is coupled to the storage elements and to the buffer circuit. Each block is checked by the check circuit using an error correcting code, and data indicating detected errors is stored in the storage elements.

Abstract: A low jitter digital frequency synthesizer includes a first counter module, a second counter module, a snapshot module, an error value generation module, and a tapped delay line. The first counter module counts intervals of M cycles of an input clock to produce a first count. The second counter module count intervals of D cycles of an output clock to produce a second count, wherein a rate of the output clock corresponds to M/D times a rate of the input clock. The snapshot module periodically takes a snapshot of the first and second counts to produce snapshots. The error value generation module generates an error value based on the snapshots. The tapped delay line module produces the output clock based on the error value.

Abstract: Method and apparatus for reducing effect of jitter is described. More particularly, one or more taps of a delay line are selected for a reference clock signal. These selected taps each have an associated index, which is stored, and stored indices are statistically processed to select a tap of another delay line.

Abstract: A configurable voltage bias circuit is used to control gate delays in buffers by adjusting the supply voltage of the buffers. The programmable voltage bias circuit includes a configurable voltage divider, which receives an input supply voltage and generates an output supply voltage, and a configurable resistance circuit, which is coupled between the configurable voltage divider and ground. By using a temperature dependent reference voltage to generate the input supply voltage, the output supply voltage is also made to be dependent upon temperature. The programmable voltage bias circuit of the present invention uses the temperature dependence of the output supply voltage to make the gate delays of the buffer temperature-independent.

Abstract: Method and apparatus are described for duty cycle determination and adjustment. More particularly, an output signal is sampled and provided to duty cycle check circuitry which characterizes the duty cycle of the sampled output signal. This characterization may be provided to a wafer prober or integrated circuit tester to determine whether duty cycle is within an acceptance range. Alternatively, the duty cycle indicator signal may be provided to drive adjustment circuitry. In response to duty cycle not being within an acceptance range, drive adjust circuitry provides a drive adjustment signal to adjust duty cycle at an output buffer by turning on one or more p-channel drive transistors, one or more n-channel drive transistors, or a combination of both. Moreover, wells may be biased responsive to a detected duty cycle in order to correct the duty cycle.