Patents by Inventor Avgerinos V. Gelatos

Avgerinos V. Gelatos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7175713
    Abstract: An apparatus for cyclical depositing of thin films on semiconductor substrates, comprising a process chamber having a gas distribution system with separate paths for process gases and an exhaust system synchronized with operation of valves dosing the process gases into a reaction region of the chamber.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: February 13, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Randhir P. S. Thakur, Alfred W. Mak, Ming Xi, Walter Benjamin Glenn, Ahmad A. Khan, Ayad A. Al-Shaikh, Avgerinos V. Gelatos, Salvador P. Umotoy
  • Publication number: 20030224217
    Abstract: A process for treating refractory metal-boron layers deposited by atomic layer deposition resulting in the formation of a ternary amorphous refractory metal-nitrogen-boron film is disclosed. The resulting ternary film remains amorphous following thermal annealing at temperatures up to 800° C. The ternary films are formed following thermal annealing in a reactive nitrogen-containing gas. Subsequent processing does not disrupt the amorphous character of the ternary film. arrangement where a blended solution is supplied to a remote point of use.
    Type: Application
    Filed: October 21, 2002
    Publication date: December 4, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Jeong Soo Byun, Alfred W. Mak, Hui Zhang, Hyungsuk Alexander Yoon, Avgerinos V. Gelatos, Robert L. Jackson, Ming Xi, Randhir P.S. Thakur
  • Publication number: 20030172872
    Abstract: An apparatus for cyclical depositing of thin films on semiconductor substrates, comprising a process chamber having a gas distribution system with separate paths for process gases and an exhaust system synchronized with operation of valves dosing the process gases into a reaction region of the chamber.
    Type: Application
    Filed: January 27, 2003
    Publication date: September 18, 2003
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Randhir P.S. Thakur, Alfred W. Mak, Ming Xi, Walter Benjamin Glenn, Ahmad A. Khan, Ayad A. Al-Shaikh, Avgerinos V. Gelatos, Salvador P. Umotoy
  • Patent number: 6174810
    Abstract: In one embodiment, a copper interconnect structure is formed by depositing a dielectric layer (28) on a semiconductor substrate (10). The dielectric layer (28) is then patterned to form interconnect openings (29). A layer of copper (34) is then formed within the interconnect openings (29). A portion of the copper layer (34) is then removed to form copper interconnects (39) within the interconnect openings (29). A copper barrier layer (40) is then formed overlying the copper interconnects (39). Adhesion between the copper barrier layer (40) and the copper interconnects (39) is improved by exposing the exposed surface of the copper interconnects (39) to a plasma generated using only ammonia as a source gas.
    Type: Grant
    Filed: April 6, 1998
    Date of Patent: January 16, 2001
    Assignee: Motorola, Inc.
    Inventors: Rabiul Islam, Avgerinos V. Gelatos, Kevin Lucas, Stanley M. Filipiak, Ramnath Venkatraman
  • Patent number: 5391517
    Abstract: A copper metallization structure and process for the formation of electrical interconnections fabricated with pure copper metal is provided. The metallization structure includes an interface layer (22) intermediate to a dielectric layer (12), and a copper interconnect (30). The interface layer (22) functions to adhere the copper interconnect (30) to a device substrate (10) and to prevent the diffusion of copper into underlying dielectric layers. The interconnect layer (22) is fabricated by depositing a first titanium layer (16) followed by the sequential deposition of a titanium nitride layer (18), and a second titanium layer (20). A copper layer (24) is deposited to overlie the second titanium layer (20) and an annealing step is carried out to form a copper-titanium intermetallic layer (26).
    Type: Grant
    Filed: September 13, 1993
    Date of Patent: February 21, 1995
    Assignee: Motorola Inc.
    Inventors: Avgerinos V. Gelatos, Robert W. Fiordalice
  • Patent number: 5324690
    Abstract: A non-silyated, ternary boron nitride film (18, 38) is provided for semiconductor device applications. The non-silyated, ternary boron nitride film is preferably formed by plasma-enhanced chemical vapor deposition using non-silyated compounds of boron, nitrogen, and either oxygen, germanium, germanium oxide, fluorine, or carbon. In one embodiment, boron oxynitride (BNO) is deposited in a plasma-enhanced chemical vapor deposition reactor using ammonia (NH.sub.3), diborane (B.sub.2 H.sub.6), and nitrous oxide (N.sub.2 O). The BNO film has a dielectric constant of about 3.3 and exhibits a negligible removal rate in a commercial polishing apparatus. Because of its low dielectric constant and high hardness, the ternary boron nitride film formed in accordance with the invention can be advantageously used as a polish-stop layer and as a interlevel dielectric layer in a semiconductor device.
    Type: Grant
    Filed: February 1, 1993
    Date of Patent: June 28, 1994
    Assignee: Motorola Inc.
    Inventors: Avgerinos V. Gelatos, Stephen S. Poon
  • Patent number: 5275973
    Abstract: Metallization having a self-aligned diffusion barrier or seed layer is formed in an integrated circuit. In one embodiment of the invention, a sacrificial material (20) is used to define a seed layer (24). A dielectric layer (26) is then formed and the sacrificial material (20) is subsequently removed to expose the underlying seed layer (24). A conductive layer of material (32), such as copper, is then selectively deposited onto the seed layer (24). Because the diffusion barrier or seed layer is self-aligned the metal to metal spacing in an integrated circuit may be reduced. Therefore, integrated circuits having high device packing densities can be fabricated.
    Type: Grant
    Filed: March 1, 1993
    Date of Patent: January 4, 1994
    Assignee: Motorola, Inc.
    Inventor: Avgerinos V. Gelatos
  • Patent number: 5064683
    Abstract: In a polish palnarization process using a polishing apparatus and an abrasive slurry, a boron nitride (BN) polish stop layer (18) is provided to increase the polish selectivity. The BN layer deposited in accordance with the invention has a hexagonal-close-pack crystal orientation and is characterized by chemical inertness and high hardness. The BN layer has a negligible polish removal rate yielding extremely high polish selectivity when used as a polish stop for polishing a number of materials commonly used in the fabrication of semiconductor devices. In accordance with the invention, a substrate (12) is provided having an uneven topography including elevated regions and recessed regions. A BN polish stop layer (18) is desposited to overlie the substrate (12) and a fill material (20, 36) which can be dielectric material or a conductive material, is deposited to overlie the BN polish stop (18) and the recessed regions of the substrate.
    Type: Grant
    Filed: October 29, 1990
    Date of Patent: November 12, 1991
    Assignee: Motorola, Inc.
    Inventors: Stephen S. Poon, Avgerinos V. Gelatos