Patents by Inventor Avinash N. Ananthakrishnan

Avinash N. Ananthakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DYNAMIC C0-STATE CACHE RESIZING
    Publication number: 20120173907
    Abstract: Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 5, 2012
    Inventors: Jaideep MOSES, Rameshkumar G. Illikkal, Ravishankar Iyer, Jared E. Bendt, Sadagopan Srinivasan, Andrew J. Herdrich, Ashish V. Choubal, Avinash N. Ananthakrishnan, Vijay S.R. Degalahal
  • Dynamically Modifying A Power/Performance Tradeoff Based On Processor Utilization
    Publication number: 20120144217
    Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 7, 2012
    Inventors: Krishnakanth V. Sistla, Mark Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Daniel Borkowski, Vivek Garg, Cagdas Akturan, Avinash N. Ananthakrishnan
  • Method, Apparatus, and System for Energy Efficiency and Energy Conservation Through Dynamic Management of Memory and Input/Output Subsystems
    Publication number: 20120095607
    Abstract: According to one embodiment of the invention, an integrated circuit device comprises an interconnect, at least one compute engine and a control unit. Coupled to the at least one compute engine via the interconnect, the control unit to analyze heuristic information from the at least one compute engine and to increase or decrease a bandwidth of the interconnect based on the heuristic information.
    Type: Application
    Filed: December 22, 2011
    Publication date: April 19, 2012
    Inventors: Ryan D. Wells, Avinash N. Ananthakrishnan, Inder Sodhi, Eric C. Samson, Joydeep Ray