Abstract: Prioritization of VT scans can be performed using particular select gates of a memory device or memory sub-system in the absence of performing such select gate scan operations on all of the select gates of an entire memory die or of all the memory dice of a memory device or memory sub-system. A method for such prioritization of VT scans includes determining quality characteristics of a memory die and altering a threshold voltage applied to the memory die in performance of a select gate scan operation based, at least in part, on the determined quality characteristics of the memory die. Such methods can further include performing the select gate scan operation by applying signaling having the altered threshold voltage to a select gate of the memory die.

Abstract: Methods, systems, and devices for memory pillar selection transistor evaluation are described. A memory system may be configured to monitor threshold voltage characteristics of pillar selection transistors, which may include evaluations relative to certain subsets of the pillar selection transistors. For example, an activation voltage may be applied to the pillar selection transistors to determine whether threshold voltages associated with each subset of pillar selection transistors have shifted. Determining whether the threshold voltages have shifted may include determining whether an access parameter has been satisfied, such as a duration to program memory cells. For example, a relatively long duration may indicate that channels associated with pillar selection transistors have become less conductive for a given activation voltage.

Abstract: Prioritization of VT scans can be performed using particular select gates of a memory device or memory sub-system in the absence of performing such select gate scan operations on all of the select gates of an entire memory die or of all the memory dice of a memory device or memory sub-system. A method for such prioritization of VT scans includes determining quality characteristics of a memory die and altering a threshold voltage applied to the memory die in performance of a select gate scan operation based, at least in part, on the determined quality characteristics of the memory die. Such methods can further include performing the select gate scan operation by applying signaling having the altered threshold voltage to a select gate of the memory die.

Abstract: Methods, systems, and devices for managing trap-up in a memory system are described. A request to erase a block of a memory device may be received. Based on the request, a scan operation for determining whether a threshold voltage distribution for a dummy word line associated with the block satisfies one or more criteria may be performed. Based on the scan operation, whether to perform one or more program and erase cycles on the block using a first voltage level for a de-biasing operation of a program and erase (P/E) cycle may be determined. The first voltage level may be lower than a second voltage level for one or more prior de-biasing operations of one or more prior P/E cycles performed on the block. The block of memory may be managed based on whether the P/E cycling with the debiasing operation having the voltage level is performed.

Abstract: A variety of applications can include memory devices designed to provide stabilization of selector devices in a memory array of the memory device. A selector stabilizer pulse can be applied to a selector device of a string of the memory array and to a memory cell of multiple memory cells of the string with the memory cell being adjacent to the selector device in the string. The selector stabilizer pulse can be applied directly following an erase operation to the string to stabilize the threshold voltage of the selector device. The selector stabilizer pulse can be applied as part of the erase algorithm of the memory device. Additional devices, systems, and methods are discussed.

Abstract: Control logic of a memory device to initiate an erase operation including a set of erase loops to erase one or more memory cells of the memory device. During a first erase loop of the set of erase loops, a first erase pulse having an erase voltage level is caused to be applied to a source line associated with the one or more memory cells. During the first erase loop, a first erase bias voltage having an initial voltage level is caused to be applied to a first select gate and a second erase bias voltage having the initial voltage level is caused to be applied to a second select gate associated with the source line, where the first erase bias voltage level is based on a first delta voltage level. During a subset of erase loops following the first erase loop, a second erase pulse having the erase voltage level is caused to be applied to the source line.

Abstract: A memory device can include a memory array coupled with a control logic. The control logic initiates a program operation on the memory array, the program operation including a program phase and a program recovery phase. The control logic causes a program voltage to be applied to a selected word line during the program phase. The control logic causes a select gate drain coupled with a string of memory cells to deactivate during the program recovery phase after applying the program voltage, where the string of memory cells include a plurality of memory cells each coupled to a corresponding word line of a plurality of wordlines. The control logic causes a voltage to be applied to a select gate source coupled with the string of memory cells to activate the select gate source during the program recovery phase concurrent to causing the select gate drain to deactivate.

Abstract: Prioritization of VT scans can be performed using particular select gates of a memory device or memory sub-system in the absence of performing such select gate scan operations on all of the select gates of an entire memory die or of all the memory dice of a memory device or memory sub-system. A method for such prioritization of VT scans includes determining quality characteristics of a memory die and altering a threshold voltage applied to the memory die in performance of a select gate scan operation based, at least in part, on the determined quality characteristics of the memory die. Such methods can further include performing the select gate scan operation by applying signaling having the altered threshold voltage to a select gate of the memory die.

Abstract: A variety of applications can include memory devices designed to provide stabilization of selector devices in a memory array of the memory device. A selector stabilizer pulse can be applied to a selector device of a string of the memory array and to a memory cell of multiple memory cells of the string with the memory cell being adjacent to the selector device in the string. The selector stabilizer pulse can be applied directly following an erase operation to the string to stabilize the threshold voltage of the selector device. The selector stabilizer pulse can be applied as part of the erase algorithm of the memory device. Additional devices, systems, and methods are discussed.

Abstract: A variety of applications can include memory devices designed to provide stabilization of selector devices in a memory array of the memory device. A selector stabilizer pulse can be applied to a selector device of a string of the memory array and to a memory cell of multiple memory cells of the string with the memory cell being adjacent to the selector device in the string. The selector stabilizer pulse can be applied directly following an erase operation to the string to stabilize the threshold voltage of the selector device. The selector stabilizer pulse can be applied as part of the erase algorithm of the memory device. Additional devices, systems, and methods are discussed.

Abstract: A processing device in a memory system receives a request to erase a data block of a memory device, determines a number of program/erase cycles performed on the data block, and performs an erase operation to erase the data block. The processing device further determines that the number of program/erase cycles performed on the data block satisfies a scan threshold condition and performs a first threshold voltage integrity scan on the data block to determine a first error rate associated with a current threshold voltage of at least one select gate device of the data block. Responsive to the first error rate associated with the current threshold voltage of the at least one select gate device satisfying an error threshold criterion, the processing device performs a touch up operation on the at least one select gate device to adjust the current threshold voltage to the target threshold voltage.

Abstract: A variety of applications can include memory devices designed to provide stabilization of selector devices in a memory array of the memory device. A selector stabilizer pulse can be applied to a selector device of a string of the memory array and to a memory cell of multiple memory cells of the string with the memory cell being adjacent to the selector device in the string. The selector stabilizer pulse can be applied directly following an erase operation to the string to stabilize the threshold voltage of the selector device. The selector stabilizer pulse can be applied as part of the erase algorithm of the memory device. Additional devices, systems, and methods are discussed.

Abstract: A processing device in a memory system receives a request to erase a data block of a memory device, determines a number of program/erase cycles performed on the data block, and performs an erase operation to erase the data block. The processing device further determines that the number of program/erase cycles performed on the data block satisfies a scan threshold condition and performs a first threshold voltage integrity scan on the data block to determine a first error rate associated with a current threshold voltage of at least one select gate device of the data block. Responsive to the first error rate associated with the current threshold voltage of the at least one select gate device satisfying an error threshold criterion, the processing device performs a touch up operation on the at least one select gate device to adjust the current threshold voltage to the target threshold voltage.

Abstract: A first entropy indicator is calculated at a first time for a collection of data stored in at least one memory. A second entropy indicator is calculated at a second time for the collection of data. The first entropy indicator is compared with the second entropy indicator. Based on the comparison, it is determined whether to back up the collection of data and/or whether to retain an earlier backup of the collection of data.

Abstract: A processing device in a memory system receives a request to erase a data block of a memory device, determines a number of program/erase cycles performed on the data block, and performs an erase operation to erase the data block. The processing device further determines that the number of program/erase cycles performed on the data block satisfies a scan threshold condition and performs a first threshold voltage integrity scan on the data block to determine a first error rate associated with a current threshold voltage of at least one select gate device of the data block. Responsive to the first error rate associated with the current threshold voltage of the at least one select gate device satisfying an error threshold criterion, the processing device performs a touch up operation on the at least one select gate device to adjust the current threshold voltage to the target threshold voltage.

Abstract: A method for detecting faults in a memory system includes performing an operation on at least one memory cell of the memory system. The method also includes receiving, during performance of the operation, a first clock cycle count for a first pulse of a charge pump associated with the at least one memory cell. The method also includes receiving, during performance of the operation, a second clock cycle count for a second pulse of the charge pump. The method also includes determining whether a fault will occur based on a difference between the first clock cycle count and the second clock cycle count.

Abstract: A method for detecting defects in a memory system includes receiving a command to perform a standard erase operation on at least one memory cell of the memory system. The method also includes performing a first defect detection operation on the at least one memory cell. The method also includes setting, in response to the first defect detection operation detecting a defect, a defect status indicator. The method also includes performing the standard erase operation on the at least one memory cell. The method also includes performing a second defect detection operation on the at least one memory cell. The method also includes setting, in response to the second defect detection operation detecting a defect, the defect status indicator.

Abstract: A Data Storage Device (DSD) or a server is set to an unlocked state to allow access to a memory of the DSD or to a DSD of the server. Communication is established with an access station using a wireless communication interface, and an access code is received from the access station via the wireless communication interface. If the received access code is determined to be valid, the DSD or server is set to the unlocked state. According to another aspect, communication is established with a DSD or a server using a wireless communication interface, and an access code is generated and sent to the DSD or the server for setting the DSD or the server to the unlocked state.

Abstract: A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

Abstract: Aspects of the disclosure provide for reducing a temperature of one or more non-volatile memory (NVM) dies of a solid state drive (SSD). The methods and apparatus detect a temperature of one or more NVM dies of a plurality of NVM dies of the SSD, the plurality of NVM dies including at least one parity NVM die, and determine that the one or more NVM dies is overheated when the detected temperature is at or above a threshold temperature. If the detected temperature is at or above the threshold temperature, the methods and apparatus redirect parity data designated for the at least one parity NVM die to the one or more overheated NVM dies. By repurposing the one more overheated NVM dies to store the parity data, the repurposed dies will experience less activity, and therefore, generate less heat without throttling or reducing the workload capability of the dies.