Patents by Inventor Avinash Srikrishnan Kashyap
Avinash Srikrishnan Kashyap has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10811494Abstract: A power transistor assembly and method of mitigating short channel effects in a power transistor assembly are provided. The power transistor assembly includes a first layer of semiconductor material formed of a first conductivity type material and a hard mask layer covering at least a portion of the first layer and having a window therethrough exposing a surface of the first layer. The power transistor assembly also includes a first region formed in the first layer of semiconductor material of a second conductivity type material and aligned with the window, one or more source regions formed of first conductivity type material within the first region and separated by a portion of the first region, and an extension of the first region extending laterally through the surface of the first layer.Type: GrantFiled: November 5, 2018Date of Patent: October 20, 2020Assignee: Microsemi CorporationInventors: Dumitru Gheorge Sdrulla, Avinash Srikrishnan Kashyap
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Patent number: 10511163Abstract: A surge suppression device includes a micro electromechanical system (MEMS) switch electrically connected to a current path. Additionally, the surge suppression device includes a transient voltage suppression (TVS) device electrically connected in series to the MEMS switch. The surge suppression device is configured to protect electronic components from voltage surges or current surges.Type: GrantFiled: December 29, 2015Date of Patent: December 17, 2019Assignee: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Christian M. Giovanniello, Christopher Fred Keimel
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Publication number: 20190140047Abstract: A power transistor assembly and method of mitigating short channel effects in a power transistor assembly are provided. The power transistor assembly includes a first layer of semiconductor material formed of a first conductivity type material and a hard mask layer covering at least a portion of the first layer and having a window therethrough exposing a surface of the first layer. The power transistor assembly also includes a first region formed in the first layer of semiconductor material of a second conductivity type material and aligned with the window, one or more source regions formed of first conductivity type material within the first region and separated by a portion of the first region, and an extension of the first region extending laterally through the surface of the first layer.Type: ApplicationFiled: November 5, 2018Publication date: May 9, 2019Inventors: Dumitru Gheorge Sdrulla, Avinash Srikrishnan Kashyap
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Patent number: 10186509Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.Type: GrantFiled: October 25, 2016Date of Patent: January 22, 2019Assignee: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, James Jay McMahon, Ljubisa Dragoljub Stevanovic
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Patent number: 10103540Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer. The TVS device also includes a conductive path electrically coupled between the second layer and an electrical connection to a circuit external to the TVS device, the conductive path configured to permit controlling a turning on of the TVS device at less than a breakdown voltage of the TVS device.Type: GrantFiled: April 24, 2014Date of Patent: October 16, 2018Assignee: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Joe Walter Kirstein, Alexander Viktorovich Bolotnikov
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Publication number: 20180190791Abstract: The present disclosure relates to a symmetrical, punch-through transient voltage suppression (TVS) device includes a mesa structure disposed on a semiconductor substrate. The mesa structure includes a first semiconductor layer of a first conductivity-type, a second semiconductor layer of a second conductivity-type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductive-type disposed on the second semiconductor layer. The mesa structure also includes beveled sidewalls forming mesa angles with respect to the semiconductor substrate and edge implants disposed at lateral edges of the second semiconductor layer. The edge implants including dopants of the second conductive-type are configured to cause punch-through to occur in a bulk region and not in the lateral edges of the second semiconductor layer.Type: ApplicationFiled: January 4, 2017Publication date: July 5, 2018Inventors: Victor Mario Torres, Reza Ghandi, David Alan Lilienfeld, Avinash Srikrishnan Kashyap, Alexander Viktorovich Bolotnikov
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Patent number: 10014388Abstract: The present disclosure relates to a symmetrical, punch-through transient voltage suppression (TVS) device includes a mesa structure disposed on a semiconductor substrate. The mesa structure includes a first semiconductor layer of a first conductivity-type, a second semiconductor layer of a second conductivity-type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductive-type disposed on the second semiconductor layer. The mesa structure also includes beveled sidewalls forming mesa angles with respect to the semiconductor substrate and edge implants disposed at lateral edges of the second semiconductor layer. The edge implants including dopants of the second conductive-type are configured to cause punch-through to occur in a bulk region and not in the lateral edges of the second semiconductor layer.Type: GrantFiled: January 4, 2017Date of Patent: July 3, 2018Assignee: GENERAL ELECTRIC COMPANYInventors: Victor Mario Torres, Reza Ghandi, David Alan Lilienfeld, Avinash Srikrishnan Kashyap, Alexander Viktorovich Bolotnikov
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Patent number: 9997507Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.Type: GrantFiled: July 25, 2013Date of Patent: June 12, 2018Assignee: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Rui Zhou, Peter Almern Losee
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Patent number: 9947647Abstract: A method of fabricating an overvoltage protection device and an over-voltage circuit protection device are provided. The over-voltage circuit protection device includes a plurality of transient voltage suppression (TVS) devices coupled in electrical parallel.Type: GrantFiled: December 11, 2013Date of Patent: April 17, 2018Assignee: GENERAL ELECTRIC COMPANYInventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Mark Gerard Roberto, David Mulford Shaddock, Joe Walter Kirstein
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Patent number: 9806157Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The TVS device includes a first layer of wide band-gap semiconductor material formed of a first conductivity type material, a second layer of wide band-gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, the second layer including a first concentration of dopant. The TVS device further including a third layer of wide band-gap semiconductor material formed of the second conductivity type material over at least a portion of the second layer, the third layer including a second concentration of dopant, the second concentration of dopant being different than the first concentration of dopant. The TVS device further including a fourth layer of wide band-gap semiconductor material formed of the first conductivity type material over at least a portion of the third layer.Type: GrantFiled: October 3, 2014Date of Patent: October 31, 2017Assignee: General Electric CompanyInventors: Alexander Viktorovich Bolotnikov, Avinash Srikrishnan Kashyap
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Publication number: 20170294434Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.Type: ApplicationFiled: October 25, 2016Publication date: October 12, 2017Inventors: Avinash Srikrishnan KASHYAP, Peter Micah SANDVIK, James Jay MCMAHON, Ljubisa Dragoljub STEVANOVIC
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Publication number: 20170187181Abstract: A surge suppression device includes a micro electromechanical system (MEMS) switch electrically connected to a current path. Additionally, the surge suppression device includes a transient voltage suppression (TVS) device electrically connected in series to the MEMS switch. The surge suppression device is configured to protect electronic components from voltage surges or current surges.Type: ApplicationFiled: December 29, 2015Publication date: June 29, 2017Inventors: Avinash Srikrishnan Kashyap, Christian M. Giovanniello, Christopher Fred Keimel
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Patent number: 9508841Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.Type: GrantFiled: August 1, 2013Date of Patent: November 29, 2016Assignee: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, James Jay McMahon, Ljubisa Dragoljub Stevanovic
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Patent number: 9379189Abstract: A transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (?m) and 22.0 ?m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.Type: GrantFiled: March 11, 2015Date of Patent: June 28, 2016Assignee: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Peter Michah Sandvik, Stephen Daley Arthur
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Publication number: 20160099318Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The TVS device includes a first layer of wide band-gap semiconductor material formed of a first conductivity type material, a second layer of wide band-gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, the second layer including a first concentration of dopant. The TVS device further including a third layer of wide band-gap semiconductor material formed of the second conductivity type material over at least a portion of the second layer, the third layer including a second concentration of dopant, the second concentration of dopant being different than the first concentration of dopant. The TVS device further including a fourth layer of wide band-gap semiconductor material formed of the first conductivity type material over at least a portion of the third layer.Type: ApplicationFiled: October 3, 2014Publication date: April 7, 2016Inventors: Alexander Viktorovich Bolotnikov, Avinash Srikrishnan Kashyap
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Publication number: 20150311701Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer. The TVS device also includes a conductive path electrically coupled between the second layer and an electrical connection to a circuit external to the TVS device, the conductive path configured to permit controlling a turning on of the TVS device at less than a breakdown voltage of the TVS device.Type: ApplicationFiled: April 24, 2014Publication date: October 29, 2015Applicant: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Joe Walter Kirstein, Alexander Viktorovich Bolotnikov
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Patent number: 9130365Abstract: A high temperature electronic system includes an electronics unit configured for exposure to an environment having a temperature greater than approximately 150.0° C. The remote electronics unit includes a transient voltage suppressor (TVS) assembly coupled in operative relationship with at least some electronic components of the electronics unit. The TVS assembly includes at least one TVS device comprising at least one of a punch-through wide band-gap semiconductor TVS die and an avalanche breakdown wide band-gap semiconductor TVS die encapsulated in a flip-chip package at least partially surrounding the die, and coupled to first and second electrodes exposed to a single side of the encapsulation.Type: GrantFiled: September 15, 2014Date of Patent: September 8, 2015Assignee: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Emad Andarawis Andarawis, David Mulford Shaddock
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Patent number: 9111750Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon carbide (SiC), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.Type: GrantFiled: June 28, 2013Date of Patent: August 18, 2015Assignee: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Rui Zhou
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Publication number: 20150187884Abstract: A transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (?m) and 22.0 ?m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.Type: ApplicationFiled: March 11, 2015Publication date: July 2, 2015Inventors: Avinash SRIKRISHNAN KASHYAP, Peter Michah SANDVIK, Stephen Daley ARTHUR
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Publication number: 20150162743Abstract: A method of fabricating an overvoltage protection device and an over-voltage circuit protection device are provided. The over-voltage circuit protection device includes a plurality of transient voltage suppression (TVS) devices coupled in electrical parallel.Type: ApplicationFiled: December 11, 2013Publication date: June 11, 2015Applicant: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Mark Gerard Roberto, David Mulford Shaddock, Joe Walter Kirstein