Patents by Inventor Avinash Srikrishnan Kashyap
Avinash Srikrishnan Kashyap has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9042072Abstract: A method of method of forming a wide band-gap semiconductor transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a connecting component configured to electrically couple a first electrical component to a second electrical component located remotely from the first electrical component through one or more electrical conduits and a transient voltage suppressor device positioned within the connecting component and electrically coupled to the one or more electrical conduits wherein the TVS device includes a wide band-gap semiconductor material.Type: GrantFiled: March 30, 2012Date of Patent: May 26, 2015Assignee: General Electric CompanyInventors: Aaron Jay Knobloch, Emad Andarawis Andarawis, Harry Kirk Mathews, Jr., Avinash Srikrishnan Kashyap
-
Patent number: 8987858Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (?m) and 22.0 ?m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.Type: GrantFiled: March 18, 2013Date of Patent: March 24, 2015Assignee: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Stephen Daley Arthur
-
Publication number: 20150034969Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.Type: ApplicationFiled: August 1, 2013Publication date: February 5, 2015Applicant: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, James Jay McMahon, Ljubisa Dragoljub Stevanovic
-
Publication number: 20150028469Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.Type: ApplicationFiled: July 25, 2013Publication date: January 29, 2015Applicant: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Rui Zhou, Peter Almern Losee
-
Publication number: 20150001551Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon carbide (SiC), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Rui Zhou
-
Publication number: 20150002976Abstract: A high temperature electronic system includes an electronics unit configured for exposure to an environment having a temperature greater than approximately 150.0° C. The remote electronics unit includes a transient voltage suppressor (TVS) assembly coupled in operative relationship with at least some electronic components of the electronics unit. The TVS assembly includes at least one TVS device comprising at least one of a punch-through wide band-gap semiconductor TVS die and an avalanche breakdown wide band-gap semiconductor TVS die encapsulated in a flip-chip package at least partially surrounding the die, and coupled to first and second electrodes exposed to a single side of the encapsulation.Type: ApplicationFiled: September 15, 2014Publication date: January 1, 2015Inventors: Avinash Srikrishnan Kashyap, Emad Andarawis Andarawis, David Mulford Shaddock
-
Publication number: 20140264775Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (?m) and 22.0 ?m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.Type: ApplicationFiled: March 18, 2013Publication date: September 18, 2014Applicant: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Stephen Daley Arthur
-
Patent number: 8835976Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The transient voltage suppressor (TVS) assembly includes a semiconductor die including a contact surface on a single side of the die, the die further including a substrate comprising a layer of at least one of an electrical insulator material, a semi-insulating material, and a first wide band gap semiconductor having a conductivity of a first polarity, at least a TVS device including a plurality of wide band gap semiconductor layers formed on the substrate; a first electrode coupled in electrical contact with the TVS device and extending to the contact surface, and a second electrode electrically coupled to the substrate extending to the contact surface.Type: GrantFiled: March 14, 2012Date of Patent: September 16, 2014Assignee: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Emad Andarawis Andarawis, David Mulford Shaddock
-
Patent number: 8765524Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.Type: GrantFiled: August 15, 2013Date of Patent: July 1, 2014Assignee: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, David Mulford Shaddock, Emad Andarawis Andarawis, Peter Micah Sandvik, Stephen Daley Arthur, Vinayak Tilak
-
Patent number: 8730629Abstract: A semiconductor die includes a substrate comprising a first layer of a first wide band gap semiconductor material having a first conductivity, a second layer of a second wide band gap semiconductor material having a second conductivity different from the first conductivity, in electrical contact with the first layer, a third layer of a third wide band gap semiconductor material having a third conductivity different from the first conductivity and second conductivity, in electrical contact with the second layer, a fourth layer of a fourth wide band gap semiconductor material having the second conductivity, in electrical contact with the third layer, and a fifth layer of a fifth wide band gap semiconductor material having the first conductivity and in electrical contact with the fourth layer, wherein the first layer, the second layer, the third layer, the fourth layer, and the fifth layer are sequentially arranged to form a structure.Type: GrantFiled: December 22, 2011Date of Patent: May 20, 2014Assignee: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Stanislav Ivanovich Soloviev
-
Publication number: 20130328064Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.Type: ApplicationFiled: August 15, 2013Publication date: December 12, 2013Applicant: GENERAL ELECTRIC COMPANYInventors: Avinash Srikrishnan Kashyap, David Mulford Shaddock, Emad Andarawis Andarawis, Peter Micah Sandvik, Stephen Daley Arthur, Vinayak Tilak
-
Publication number: 20130258541Abstract: A method of method of forming a wide band-gap semiconductor transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a connecting component configured to electrically couple a first electrical component to a second electrical component located remotely from the first electrical component through one or more electrical conduits and a transient voltage suppressor device positioned within the connecting component and electrically coupled to the one or more electrical conduits wherein the TVS device includes a wide band-gap semiconductor material.Type: ApplicationFiled: March 30, 2012Publication date: October 3, 2013Inventors: Aaron Jay Knobloch, Emad Andarawis Andarawis, Harry Kirk Mathews, JR., Avinash Srikrishnan Kashyap
-
Publication number: 20130240903Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The transient voltage suppressor (TVS) assembly includes a semiconductor die including a contact surface on a single side of the die, the die further including a substrate comprising a layer of at least one of an electrical insulator material, a semi-insulating material, and a first wide band gap semiconductor having a conductivity of a first polarity, at least a TVS device including a plurality of wide band gap semiconductor layers formed on the substrate; a first electrode coupled in electrical contact with the TVS device and extending to the contact surface, and a second electrode electrically coupled to the substrate extending to the contact surface.Type: ApplicationFiled: March 14, 2012Publication date: September 19, 2013Inventors: Avinash Srikrishnan Kashyap, Emad Andarawis Andarawis, David Mulford Shaddock
-
Patent number: 8530902Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.Type: GrantFiled: October 26, 2011Date of Patent: September 10, 2013Assignee: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, David Mulford Shaddock, Emad Andarawis Andarawis, Peter Micah Sandvik, Stephen Daley Arthur, Vinayak Tilak
-
Publication number: 20130163139Abstract: A semiconductor die includes a substrate comprising a first layer of a first wide band gap semiconductor material having a first conductivity, a second layer of a second wide band gap semiconductor material having a second conductivity different from the first conductivity, in electrical contact with the first layer, a third layer of a third wide band gap semiconductor material having a third conductivity different from the first conductivity and second conductivity, in electrical contact with the second layer, a fourth layer of a fourth wide band gap semiconductor material having the second conductivity, in electrical contact with the third layer, and a fifth layer of a fifth wide band gap semiconductor material having the first conductivity and in electrical contact with the fourth layer, wherein the first layer, the second layer, the third layer, the fourth layer, and the fifth layer are sequentially arranged to form a structure.Type: ApplicationFiled: December 22, 2011Publication date: June 27, 2013Applicant: GENERAL ELECTRIC COMPANYInventors: Avinash Srikrishnan Kashyap, Stanislav Ivanovich Soloviev
-
Publication number: 20130105816Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.Type: ApplicationFiled: October 26, 2011Publication date: May 2, 2013Inventors: Avinash Srikrishnan Kashyap, David Mulford Shaddock, Emad Andarawis Andarawis, Peter Micah Sandvik, Stephen Daley Arthur, Vinayak Tilak